/**
 * Copyright (c) 2019 - 2021, Realmega Micro
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this
 *    list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form, except as embedded into a Realmega
 *    Micro integrated circuit in a product or a software update for
 *    such product, must reproduce the above copyright notice, this list of
 *    conditions and the following disclaimer in the documentation and/or other
 *    materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived from this
 *    software without specific prior written permission.
 *
 * 4. Any software provided in binary form under this license must not be reverse
 *    engineered, decompiled, modified and/or disassembled.
 *
 * Third party software included in this distribution is subject to the
 * additional license terms as defined in the /docs/licenses directory.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/**
 *****************************************************************************
 * @file    _reg_pmu_ctrl.h
 *
 * @brief    -
 *
 *****************************************************************************
*/

#ifndef __REG_PMU_CTRL_H__
#define __REG_PMU_CTRL_H__

#include "type_def.h"



//MACROS of register pm_fsm_status
#define PMU_CTRL_PM_FSM_STATUS_PD_MEM_GRP5                                    (1<<20)
#define PMU_CTRL_PM_FSM_STATUS_DA_DCDC_BUCK_EN                                (1<<19)
#define PMU_CTRL_PM_FSM_STATUS_XTAL_READY                                     (1<<18)
#define PMU_CTRL_PM_FSM_STATUS_RSTB_DBB                                       (1<<17)
#define PMU_CTRL_PM_FSM_STATUS_VRTC_OUT_SEL                                   (1<<16)
#define PMU_CTRL_PM_FSM_STATUS_PD_AON_SLEEP                                   (1<<15)
#define PMU_CTRL_PM_FSM_STATUS_PD_EM1                                         (1<<14)
#define PMU_CTRL_PM_FSM_STATUS_PD_EM0                                         (1<<13)
#define PMU_CTRL_PM_FSM_STATUS_PD_MEM_GRP4                                    (1<<12)
#define PMU_CTRL_PM_FSM_STATUS_PD_MEM_GRP3                                    (1<<11)
#define PMU_CTRL_PM_FSM_STATUS_PD_MEM_GRP2                                    (1<<10)
#define PMU_CTRL_PM_FSM_STATUS_PD_MEM_GRP1                                    (1<<9)
#define PMU_CTRL_PM_FSM_STATUS_PD_MEM_GRP0                                    (1<<8)
#define PMU_CTRL_PM_FSM_STATUS_DA_DCDC_LDO_EN                                 (1<<7)
#define PMU_CTRL_PM_FSM_STATUS_DA_XTAL_EN                                     (1<<6)
#define PMU_CTRL_PM_FSM_STATUS_DA_BG_EN                                       (1<<5)
#define PMU_CTRL_PM_FSM_STATUS_DA_LDO_VSPI_EN                                 (1<<4)
#define PMU_CTRL_PM_FSM_STATUS_PM_FSM_STATE_MASK                              (0xFUL)
#define PMU_CTRL_PM_FSM_STATUS_PM_FSM_STATE(N)                                (((N)<<0)&0xFUL)


//MACROS of register pwr_sys_ctrl
#define PMU_CTRL_PWR_SYS_CTRL_I2CS_RELEASE                                    (1<<30)
#define PMU_CTRL_PWR_SYS_CTRL_VBAT_MONIT_EN                                   (1<<29)
#define PMU_CTRL_PWR_SYS_CTRL_LOWBAT_DET_EN                                   (1<<28)
#define PMU_CTRL_PWR_SYS_CTRL_I2CS_DISABLE                                    (1<<27)
#define PMU_CTRL_PWR_SYS_CTRL_AONSLEEP_RESET_BYPASS                           (1<<26)
#define PMU_CTRL_PWR_SYS_CTRL_RESET_RELEASE_DLY_EN                            (1<<25)
#define PMU_CTRL_PWR_SYS_CTRL_PD_INTERVAL_SEL_MASK                            (0x1800000UL)
#define PMU_CTRL_PWR_SYS_CTRL_PD_INTERVAL_SEL(N)                              (((N)<<23)&0x1800000UL)
#define PMU_CTRL_PWR_SYS_CTRL_BG_EN_DLY_MASK                                  (0x600000UL)
#define PMU_CTRL_PWR_SYS_CTRL_BG_EN_DLY(N)                                    (((N)<<21)&0x600000UL)
#define PMU_CTRL_PWR_SYS_CTRL_CLK_RTC_SEL_MASK                                (0x180000UL)
#define PMU_CTRL_PWR_SYS_CTRL_CLK_RTC_SEL(N)                                  (((N)<<19)&0x180000UL)
#define PMU_CTRL_PWR_SYS_CTRL_DCDC_LDO_EN_DLY_MASK                            (0x60000UL)
#define PMU_CTRL_PWR_SYS_CTRL_DCDC_LDO_EN_DLY(N)                              (((N)<<17)&0x60000UL)
#define PMU_CTRL_PWR_SYS_CTRL_XTAL_RDY_TIME_SEL_MASK                          (0x1E000UL)
#define PMU_CTRL_PWR_SYS_CTRL_XTAL_RDY_TIME_SEL(N)                            (((N)<<13)&0x1E000UL)
#define PMU_CTRL_PWR_SYS_CTRL_RESET_DLY_TIME_SEL_MASK                         (0x1C00UL)
#define PMU_CTRL_PWR_SYS_CTRL_RESET_DLY_TIME_SEL(N)                           (((N)<<10)&0x1C00UL)
#define PMU_CTRL_PWR_SYS_CTRL_CLK_BT_SEL_MASK                                 (0x300UL)
#define PMU_CTRL_PWR_SYS_CTRL_CLK_BT_SEL(N)                                   (((N)<<8)&0x300UL)
#define PMU_CTRL_PWR_SYS_CTRL_LDO_VSPI_EN_DLY_MASK                            (0xE0UL)
#define PMU_CTRL_PWR_SYS_CTRL_LDO_VSPI_EN_DLY(N)                              (((N)<<5)&0xE0UL)
#define PMU_CTRL_PWR_SYS_CTRL_LOWBAT_OFF_BYPASS                               (1<<4)
#define PMU_CTRL_PWR_SYS_CTRL_BOR_RESET_BYPASS                                (1<<3)
#define PMU_CTRL_PWR_SYS_CTRL_WAIT_XTAL_READY_EN                              (1<<2)
#define PMU_CTRL_PWR_SYS_CTRL_PM_REG_MASK                                     (0x3UL)
#define PMU_CTRL_PWR_SYS_CTRL_PM_REG(N)                                       (((N)<<0)&0x3UL)


//MACROS of register pm_fsm_ctrl
#define PMU_CTRL_PM_FSM_CTRL_LDO_VDIG_EN_DR                                   (1<<17)
#define PMU_CTRL_PM_FSM_CTRL_LDO_VDIG_EN_REG                                  (1<<16)
#define PMU_CTRL_PM_FSM_CTRL_DCDC_BUCK_EN_DR                                  (1<<15)
#define PMU_CTRL_PM_FSM_CTRL_DCDC_BUCK_EN_REG                                 (1<<14)
#define PMU_CTRL_PM_FSM_CTRL_VRTC_OUT_SEL_DR                                  (1<<13)
#define PMU_CTRL_PM_FSM_CTRL_VRTC_OUT_SEL_REG                                 (1<<12)
#define PM_FSM_CTRL_PMU_CTRL_SOFT_RESETN_BYPASS                               (1<<11)
#define PM_FSM_CTRL_PMU_CTRL_SOFT_RESETN                                      (1<<10)
#define PMU_CTRL_PM_FSM_CTRL_PD_AON_SLEEP_DR                                  (1<<9)
#define PMU_CTRL_PM_FSM_CTRL_PD_AON_SLEEP_REG                                 (1<<8)
#define PMU_CTRL_PM_FSM_CTRL_RSTB_DBB_DR                                      (1<<7)
#define PMU_CTRL_PM_FSM_CTRL_RSTB_DBB_REG                                     (1<<6)
#define PMU_CTRL_PM_FSM_CTRL_DCDC_LDO_EN_DR                                   (1<<5)
#define PMU_CTRL_PM_FSM_CTRL_DCDC_LDO_EN_REG                                  (1<<4)
#define PMU_CTRL_PM_FSM_CTRL_BG_EN_DR                                         (1<<3)
#define PMU_CTRL_PM_FSM_CTRL_BG_EN_REG                                        (1<<2)
#define PMU_CTRL_PM_FSM_CTRL_IREF_LOCAL_EN_DR                                 (1<<1)
#define PMU_CTRL_PM_FSM_CTRL_IREF_LOCAL_EN_REG                                (1<<0)


//MACROS of register xtal_clk32k_div
#define PMU_CTRL_XTAL_CLK32K_DIV_XTAL_LPN_EN                                  (1<<31)
#define PMU_CTRL_XTAL_CLK32K_DIV_CLK32K_DIV_EN                                (1<<20)
#define PMU_CTRL_XTAL_CLK32K_DIV_DIV_LP_MODE_H_DR                             (1<<19)
#define PMU_CTRL_XTAL_CLK32K_DIV_DIV_LP_MODE_H_REG                            (1<<18)
#define PMU_CTRL_XTAL_CLK32K_DIV_DIV_LP_MODE_H                                (1<<17)
#define PMU_CTRL_XTAL_CLK32K_DIV_STEP_OFFSET_UPDATE                           (1<<16)
#define PMU_CTRL_XTAL_CLK32K_DIV_STEP_OFFSET_NORMAL_MASK                      (0xFF00UL)
#define PMU_CTRL_XTAL_CLK32K_DIV_STEP_OFFSET_NORMAL(N)                        (((N)<<8)&0xFF00UL)
#define PMU_CTRL_XTAL_CLK32K_DIV_STEP_OFFSET_LP_MASK                          (0xFFUL)
#define PMU_CTRL_XTAL_CLK32K_DIV_STEP_OFFSET_LP(N)                            (((N)<<0)&0xFFUL)


//MACROS of register xtal_cfg_ctrl0
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_DOUBLER_DELAY_SEL                        (1<<31)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_DOUBLER_CLK_EDGE_SEL                     (1<<30)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_DOUBLER_EN                               (1<<29)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_CAP_COARSE_MASK                          (0x1E000000UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_CAP_COARSE(N)                            (((N)<<25)&0x1E000000UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_LP_MODE_HW_EN                            (1<<24)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_LP_MODE_DR                               (1<<23)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_LP_MODE_REG                              (1<<22)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_GM_BOOST_EN                              (1<<21)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_FIXIB_EN                                 (1<<20)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_FIX_IBIT_MASK                            (0xFC000UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_FIX_IBIT(N)                              (((N)<<14)&0xFC000UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_BUF_DRV_BIT_MASK                         (0x3800UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_BUF_DRV_BIT(N)                           (((N)<<11)&0x3800UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_VAMP_BIT_MASK                            (0x780UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_VAMP_BIT(N)                              (((N)<<7)&0x780UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_LDO_VBIT_MASK                            (0x70UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_LDO_VBIT(N)                              (((N)<<4)&0x70UL)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_PWR_SEL_DR                               (1<<3)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_PWR_SEL_REG                              (1<<2)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_EN_DR                                    (1<<1)
#define PMU_CTRL_XTAL_CFG_CTRL0_XTAL_EN_REG                                   (1<<0)


//MACROS of register xtal_cfg_ctrl1
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_CLK2DIG_EN                               (1<<31)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_AUTO_CFG                                 (1<<30)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_FIX_IBIT_XTAL_TYPE3_MASK                 (0x3F000000UL)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_FIX_IBIT_XTAL_TYPE3(N)                   (((N)<<24)&0x3F000000UL)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_FIX_IBIT_XTAL_TYPE2_MASK                 (0xFC0000UL)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_FIX_IBIT_XTAL_TYPE2(N)                   (((N)<<18)&0xFC0000UL)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_FIX_IBIT_XTAL_TYPE1_MASK                 (0x3F000UL)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_FIX_IBIT_XTAL_TYPE1(N)                   (((N)<<12)&0x3F000UL)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_FIX_IBIT_XTAL_TYPE0_MASK                 (0xFC0UL)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_FIX_IBIT_XTAL_TYPE0(N)                   (((N)<<6)&0xFC0UL)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_CAP_FINE_MASK                            (0x3FUL)
#define PMU_CTRL_XTAL_CFG_CTRL1_XTAL_CAP_FINE(N)                              (((N)<<0)&0x3FUL)


//MACROS of register pwr_base_cfg
#define PMU_CTRL_PWR_BASE_CFG_VRTC_VBIT_FORCE                                 (1<<31)
#define PMU_CTRL_PWR_BASE_CFG_VRTC_VBIT_LP_MASK                               (0x78000000UL)
#define PMU_CTRL_PWR_BASE_CFG_VRTC_VBIT_LP(N)                                 (((N)<<27)&0x78000000UL)
#define PMU_CTRL_PWR_BASE_CFG_IREF_LOCAL_PTAT_EN                              (1<<26)
#define PMU_CTRL_PWR_BASE_CFG_LOWBAT_VTH_BIT_MASK                             (0x3000000UL)
#define PMU_CTRL_PWR_BASE_CFG_LOWBAT_VTH_BIT(N)                               (((N)<<24)&0x3000000UL)
#define PMU_CTRL_PWR_BASE_CFG_LDO_VDIG_VBIT_MASK                              (0xF00000UL)
#define PMU_CTRL_PWR_BASE_CFG_LDO_VDIG_VBIT(N)                                (((N)<<20)&0xF00000UL)
#define PMU_CTRL_PWR_BASE_CFG_VRTC_ANTI_OVERSHOOT_EN                          (1<<19)
#define PMU_CTRL_PWR_BASE_CFG_VRTC_DECAP_MODE                                 (1<<18)
#define PMU_CTRL_PWR_BASE_CFG_VRTC_VBIT_MASK                                  (0x3C000UL)
#define PMU_CTRL_PWR_BASE_CFG_VRTC_VBIT(N)                                    (((N)<<14)&0x3C000UL)
#define PMU_CTRL_PWR_BASE_CFG_BYPASS_VRTC2VCORE                               (1<<13)
#define PMU_CTRL_PWR_BASE_CFG_VBAT_BOR_VTH_MASK                               (0x1C00UL)
#define PMU_CTRL_PWR_BASE_CFG_VBAT_BOR_VTH(N)                                 (((N)<<10)&0x1C00UL)
#define PMU_CTRL_PWR_BASE_CFG_VBAT_BOR_EN                                     (1<<9)
#define PMU_CTRL_PWR_BASE_CFG_HIGHV_LDO_HPMODE_MASK                           (0x180UL)
#define PMU_CTRL_PWR_BASE_CFG_HIGHV_LDO_HPMODE(N)                             (((N)<<7)&0x180UL)
#define PMU_CTRL_PWR_BASE_CFG_HIGHV_LDO_LPMODE_MASK                           (0x60UL)
#define PMU_CTRL_PWR_BASE_CFG_HIGHV_LDO_LPMODE(N)                             (((N)<<5)&0x60UL)
#define PMU_CTRL_PWR_BASE_CFG_HIGHV_LDO_ANTISHOOT_EN                          (1<<1)
#define PMU_CTRL_PWR_BASE_CFG_HIGHV_LDO_DISCHARGE_EN                          (1<<0)


//MACROS of register buck_ctrl
#define PMU_CTRL_BUCK_CTRL_DCDC_LDO_CAPLESS_EN                                (1<<10)
#define PMU_CTRL_BUCK_CTRL_DCDC_DISCHARGE_EN                                  (1<<9)
#define PMU_CTRL_BUCK_CTRL_DCDC_LDO_LPMODE                                    (1<<8)
#define PMU_CTRL_BUCK_CTRL_DCDC_VOUT_BIT_MASK                                 (0xF0UL)
#define PMU_CTRL_BUCK_CTRL_DCDC_VOUT_BIT(N)                                   (((N)<<4)&0xF0UL)
#define PMU_CTRL_BUCK_CTRL_DCDC_SOFTSTART_EN                                  (1<<3)
#define PMU_CTRL_BUCK_CTRL_DCDC_LDO_CC_EN                                     (1<<2)
#define PMU_CTRL_BUCK_CTRL_DCDC_LDO_CLMIT_CC_SEL                              (1<<1)
#define PMU_CTRL_BUCK_CTRL_DCDC_BUCK_SEL                                      (1<<0)


//MACROS of register ldo_vspi_ctrl
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VSPI_CAPLESS_EN                            (1<<12)
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VSPI_VSEL_REG                              (1<<11)
#define PMU_CTRL_LDO_VSPI_CTRL_VIOMUX_EN                                      (1<<10)
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VIO_ULP_EN                                 (1<<9)
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VIO_ULP_ANTIOS_EN                          (1<<8)
#define PMU_CTRL_LDO_VSPI_CTRL_VIO_SOURCE_SEL                                 (1<<7)
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VSPI_VBIT_MASK                             (0x70UL)
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VSPI_VBIT(N)                               (((N)<<4)&0x70UL)
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VSPI_LPMODE                                (1<<3)
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VSPI_CC_EN                                 (1<<2)
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VSPI_CLMIT_CC_SEL                          (1<<1)
#define PMU_CTRL_LDO_VSPI_CTRL_LDO_VSPI_EN_REG                                (1<<0)


//MACROS of register ana_status
#define PMU_CTRL_ANA_STATUS_BORDET_OUT                                        (1<<1)
#define PMU_CTRL_ANA_STATUS_LOWBAT_DET_OUT                                    (1<<0)


//MACROS of register pmu_ana_rsvd


//MACROS of register sw_rsvd
#define PMU_CTRL_SW_RSVD_RSVD_FOR_FUTURE_MASK                                 (0xFEUL)
#define PMU_CTRL_SW_RSVD_RSVD_FOR_FUTURE(N)                                   (((N)<<1)&0xFEUL)
#define PMU_CTRL_SW_RSVD_GPADC_CALIB_TYPE                                     (1<<0)


//MACROS of register misc_ctrl
#define PMU_CTRL_MISC_CTRL_BOOT_MODE_FORCE                                    (1<<30)
#define PMU_CTRL_MISC_CTRL_BOOT_MODE_REG                                      (1<<29)
#define PMU_CTRL_MISC_CTRL_CLK_IR_SEL_MASK                                    (0x18000000UL)
#define PMU_CTRL_MISC_CTRL_CLK_IR_SEL(N)                                      (((N)<<27)&0x18000000UL)
#define PMU_CTRL_MISC_CTRL_PM0_PD_XTAL                                        (1<<26)
#define PMU_CTRL_MISC_CTRL_RAM_LS_DS_DR_MASK                                  (0x3F00000UL)
#define PMU_CTRL_MISC_CTRL_RAM_LS_DS_DR(N)                                    (((N)<<20)&0x3F00000UL)
#define PMU_CTRL_MISC_CTRL_RAM_LS_REG_MASK                                    (0xFC000UL)
#define PMU_CTRL_MISC_CTRL_RAM_LS_REG(N)                                      (((N)<<14)&0xFC000UL)
#define PMU_CTRL_MISC_CTRL_RAM_DS_REG_MASK                                    (0x3F00UL)
#define PMU_CTRL_MISC_CTRL_RAM_DS_REG(N)                                      (((N)<<8)&0x3F00UL)
#define PMU_CTRL_MISC_CTRL_EM_LS_REG_MASK                                     (0xC0UL)
#define PMU_CTRL_MISC_CTRL_EM_LS_REG(N)                                       (((N)<<6)&0xC0UL)
#define PMU_CTRL_MISC_CTRL_EM_DS_REG_MASK                                     (0x30UL)
#define PMU_CTRL_MISC_CTRL_EM_DS_REG(N)                                       (((N)<<4)&0x30UL)
#define PMU_CTRL_MISC_CTRL_XTAL_TYPE_REG_MASK                                 (0xCUL)
#define PMU_CTRL_MISC_CTRL_XTAL_TYPE_REG(N)                                   (((N)<<2)&0xCUL)
#define PMU_CTRL_MISC_CTRL_EN_KP_GATING_CLK                                   (1<<1)
#define PMU_CTRL_MISC_CTRL_DIV_CNT_DISABLE                                    (1<<0)


//MACROS of register sys_ctrl_protect
#define PMU_CTRL_SYS_CTRL_PROTECT_SYS_CTRL_LOCK                               (1<<0)


//MACROS of register pmu_ctrl_protect
#define PMU_CTRL_PROTECT_PMU_CTRL_LOCK                                        (1<<0)


//MACROS of register pd_sys_frc_ctr
#define PMU_CTRL_PD_SYS_FRC_CTR_MEM_GRP5_ON                                   (1<<31)
#define PMU_CTRL_PD_SYS_FRC_CTR_RF_RETENTION_EN                               (1<<30)
#define PMU_CTRL_PD_SYS_FRC_CTR_MCU_RETENTION_EN                              (1<<29)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_BTRF_VDDG_DR                               (1<<28)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_BTRF_VDDG_REG                              (1<<27)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MCU_VDDG_DR                                (1<<26)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MCU_VDDG_REG                               (1<<25)
#define PMU_CTRL_PD_SYS_FRC_CTR_EM1_ISO                                       (1<<24)
#define PMU_CTRL_PD_SYS_FRC_CTR_EM0_ISO                                       (1<<23)
#define PMU_CTRL_PD_SYS_FRC_CTR_MEM_DS_MODE                                   (1<<22)
#define PMU_CTRL_PD_SYS_FRC_CTR_MEM_LS_MODE                                   (1<<21)
#define PMU_CTRL_PD_SYS_FRC_CTR_EM1_ON                                        (1<<20)
#define PMU_CTRL_PD_SYS_FRC_CTR_EM0_ON                                        (1<<19)
#define PMU_CTRL_PD_SYS_FRC_CTR_MEM_GRP4_ON                                   (1<<18)
#define PMU_CTRL_PD_SYS_FRC_CTR_MEM_GRP3_ON                                   (1<<17)
#define PMU_CTRL_PD_SYS_FRC_CTR_MEM_GRP2_ON                                   (1<<16)
#define PMU_CTRL_PD_SYS_FRC_CTR_MEM_GRP1_ON                                   (1<<15)
#define PMU_CTRL_PD_SYS_FRC_CTR_MEM_GRP0_ON                                   (1<<14)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_EM1_DR                                     (1<<13)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_EM1_REG                                    (1<<12)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_EM0_DR                                     (1<<11)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_EM0_REG                                    (1<<10)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP4_DR                                (1<<9)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP4_REG                               (1<<8)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP3_DR                                (1<<7)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP3_REG                               (1<<6)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP2_DR                                (1<<5)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP2_REG                               (1<<4)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP1_DR                                (1<<3)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP1_REG                               (1<<2)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP0_DR                                (1<<1)
#define PMU_CTRL_PD_SYS_FRC_CTR_PD_MEM_GRP0_REG                               (1<<0)


//MACROS of register iomux_cfg0
#define PMU_CTRL_IOMUX_CFG0_KP_OUT_POLARITY                                   (1<<27)
#define PMU_CTRL_IOMUX_CFG0_KP_IN_POLARITY                                    (1<<26)
#define PMU_CTRL_IOMUX_CFG0_KP_WAKEUP_SEL                                     (1<<25)
#define PMU_CTRL_IOMUX_CFG0_GPIO_WAKEUP_POLARITY_2_MASK                       (0x300000UL)
#define PMU_CTRL_IOMUX_CFG0_GPIO_WAKEUP_POLARITY_2(N)                         (((N)<<20)&0x300000UL)
#define PMU_CTRL_IOMUX_CFG0_GPIO_WAKEUP_POLARITY_MASK                         (0x7FFFUL)
#define PMU_CTRL_IOMUX_CFG0_GPIO_WAKEUP_POLARITY(N)                           (((N)<<0)&0x7FFFUL)


//MACROS of register iomux_cfg1
#define PMU_CTRL_IOMUX_CFG1_GPIO21_FUNC_SEL                                   (1<<20)
#define PMU_CTRL_IOMUX_CFG1_GPIO20_FUNC_SEL                                   (1<<19)
#define PMU_CTRL_IOMUX_CFG1_GPIO14_FUNC_SEL                                   (1<<18)
#define PMU_CTRL_IOMUX_CFG1_GPIO13_FUNC_SEL                                   (1<<17)
#define PMU_CTRL_IOMUX_CFG1_GPIO12_FUNC_SEL                                   (1<<16)
#define PMU_CTRL_IOMUX_CFG1_GPIO11_FUNC_SEL                                   (1<<15)
#define PMU_CTRL_IOMUX_CFG1_GPIO10_FUNC_SEL                                   (1<<14)
#define PMU_CTRL_IOMUX_CFG1_GPIO9_FUNC_SEL_MASK                               (0x3000UL)
#define PMU_CTRL_IOMUX_CFG1_GPIO9_FUNC_SEL(N)                                 (((N)<<12)&0x3000UL)
#define PMU_CTRL_IOMUX_CFG1_GPIO8_FUNC_SEL                                    (1<<11)
#define PMU_CTRL_IOMUX_CFG1_GPIO7_FUNC_SEL                                    (1<<10)
#define PMU_CTRL_IOMUX_CFG1_GPIO6_FUNC_SEL                                    (1<<9)
#define PMU_CTRL_IOMUX_CFG1_GPIO5_FUNC_SEL                                    (1<<8)
#define PMU_CTRL_IOMUX_CFG1_GPIO4_FUNC_SEL_MASK                               (0xC0UL)
#define PMU_CTRL_IOMUX_CFG1_GPIO4_FUNC_SEL(N)                                 (((N)<<6)&0xC0UL)
#define PMU_CTRL_IOMUX_CFG1_GPIO3_FUNC_SEL_MASK                               (0x30UL)
#define PMU_CTRL_IOMUX_CFG1_GPIO3_FUNC_SEL(N)                                 (((N)<<4)&0x30UL)
#define PMU_CTRL_IOMUX_CFG1_GPIO2_FUNC_SEL_MASK                               (0xCUL)
#define PMU_CTRL_IOMUX_CFG1_GPIO2_FUNC_SEL(N)                                 (((N)<<2)&0xCUL)
#define PMU_CTRL_IOMUX_CFG1_GPIO1_FUNC_SEL                                    (1<<1)
#define PMU_CTRL_IOMUX_CFG1_GPIO0_FUNC_SEL                                    (1<<0)


//MACROS of register iomux_cfg2
#define PMU_CTRL_IOMUX_CFG2_PDN_GPIO_AON_2_MASK                               (0x300000UL)
#define PMU_CTRL_IOMUX_CFG2_PDN_GPIO_AON_2(N)                                 (((N)<<20)&0x300000UL)
#define PMU_CTRL_IOMUX_CFG2_PDN_GPIO_AON_MASK                                 (0x7FFFUL)
#define PMU_CTRL_IOMUX_CFG2_PDN_GPIO_AON(N)                                   (((N)<<0)&0x7FFFUL)


//MACROS of register iomux_cfg3
#define PMU_CTRL_IOMUX_CFG3_PULLUP_GPIO_AON_2_MASK                            (0x300000UL)
#define PMU_CTRL_IOMUX_CFG3_PULLUP_GPIO_AON_2(N)                              (((N)<<20)&0x300000UL)
#define PMU_CTRL_IOMUX_CFG3_PULLUP_GPIO_AON_MASK                              (0x7FFFUL)
#define PMU_CTRL_IOMUX_CFG3_PULLUP_GPIO_AON(N)                                (((N)<<0)&0x7FFFUL)


//MACROS of register iomux_cfg4
#define PMU_CTRL_IOMUX_CFG4_PULLDN_GPIO_AON_2_MASK                            (0x300000UL)
#define PMU_CTRL_IOMUX_CFG4_PULLDN_GPIO_AON_2(N)                              (((N)<<20)&0x300000UL)
#define PMU_CTRL_IOMUX_CFG4_PULLDN_GPIO_AON_MASK                              (0x7FFFUL)
#define PMU_CTRL_IOMUX_CFG4_PULLDN_GPIO_AON(N)                                (((N)<<0)&0x7FFFUL)


//MACROS of register iomux_cfg5
#define PMU_CTRL_IOMUX_CFG5_GPIO14_IBIT_AON_MASK                              (0x30000000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO14_IBIT_AON(N)                                (((N)<<28)&0x30000000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO13_IBIT_AON_MASK                              (0xC000000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO13_IBIT_AON(N)                                (((N)<<26)&0xC000000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO12_IBIT_AON_MASK                              (0x3000000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO12_IBIT_AON(N)                                (((N)<<24)&0x3000000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO11_IBIT_AON_MASK                              (0xC00000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO11_IBIT_AON(N)                                (((N)<<22)&0xC00000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO10_IBIT_AON_MASK                              (0x300000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO10_IBIT_AON(N)                                (((N)<<20)&0x300000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO9_IBIT_AON_MASK                               (0xC0000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO9_IBIT_AON(N)                                 (((N)<<18)&0xC0000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO8_IBIT_AON_MASK                               (0x30000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO8_IBIT_AON(N)                                 (((N)<<16)&0x30000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO7_IBIT_AON_MASK                               (0xC000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO7_IBIT_AON(N)                                 (((N)<<14)&0xC000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO6_IBIT_AON_MASK                               (0x3000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO6_IBIT_AON(N)                                 (((N)<<12)&0x3000UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO5_IBIT_AON_MASK                               (0xC00UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO5_IBIT_AON(N)                                 (((N)<<10)&0xC00UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO4_IBIT_AON_MASK                               (0x300UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO4_IBIT_AON(N)                                 (((N)<<8)&0x300UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO3_IBIT_AON_MASK                               (0xC0UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO3_IBIT_AON(N)                                 (((N)<<6)&0xC0UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO2_IBIT_AON_MASK                               (0x30UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO2_IBIT_AON(N)                                 (((N)<<4)&0x30UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO1_IBIT_AON_MASK                               (0xCUL)
#define PMU_CTRL_IOMUX_CFG5_GPIO1_IBIT_AON(N)                                 (((N)<<2)&0xCUL)
#define PMU_CTRL_IOMUX_CFG5_GPIO0_IBIT_AON_MASK                               (0x3UL)
#define PMU_CTRL_IOMUX_CFG5_GPIO0_IBIT_AON(N)                                 (((N)<<0)&0x3UL)


//MACROS of register lpcomp_ctrl
#define PMU_CTRL_LPCOMP_CTRL_LPCOMP_OUT                                       (1<<12)
#define PMU_CTRL_LPCOMP_CTRL_LPCOMP_WAKEUP_MODE_MASK                          (0xC00UL)
#define PMU_CTRL_LPCOMP_CTRL_LPCOMP_WAKEUP_MODE(N)                            (((N)<<10)&0xC00UL)
#define PMU_CTRL_LPCOMP_CTRL_LPCOMP_EN                                        (1<<9)
#define PMU_CTRL_LPCOMP_CTRL_LPCOMP_RESET                                     (1<<8)
#define PMU_CTRL_LPCOMP_CTRL_LPCOMP_CH_SEL_MASK                               (0xE0UL)
#define PMU_CTRL_LPCOMP_CTRL_LPCOMP_CH_SEL(N)                                 (((N)<<5)&0xE0UL)
#define PMU_CTRL_LPCOMP_CTRL_LPCOMP_VREF_SEL_MASK                             (0x1FUL)
#define PMU_CTRL_LPCOMP_CTRL_LPCOMP_VREF_SEL(N)                               (((N)<<0)&0x1FUL)


//MACROS of register lpo32k_xtal32k_ctrl
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_XTAL32K_CBIT_MASK                        (0x3E000UL)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_XTAL32K_CBIT(N)                          (((N)<<13)&0x3E000UL)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_XTAL32K_IBIAS_BIT_MASK                   (0x1C00UL)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_XTAL32K_IBIAS_BIT(N)                     (((N)<<10)&0x1C00UL)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_XTAL32K_EN                               (1<<9)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_LPO32K_RBIT_MASK                         (0x1F0UL)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_LPO32K_RBIT(N)                           (((N)<<4)&0x1F0UL)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_LPO32K_LDO_VBIT_MASK                     (0xCUL)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_LPO32K_LDO_VBIT(N)                       (((N)<<2)&0xCUL)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_LPO32K_LDO_EN                            (1<<1)
#define PMU_CTRL_LPO32K_XTAL32K_CTRL_LPO32K_EN_REG                            (1<<0)


//MACROS of register rtc_calib_ctrl0
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_SWITCH_MODE                        (1<<30)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_CLK_SEL                            (1<<23)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_TRIG_MODE                          (1<<22)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_TIME_SEL_MASK                      (0x3C0000UL)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_TIME_SEL(N)                        (((N)<<18)&0x3C0000UL)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_INTERVAL_HOUR_MASK                 (0x3E000UL)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_INTERVAL_HOUR(N)                   (((N)<<13)&0x3E000UL)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_INTERVAL_MINUTE_MASK               (0x1F80UL)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_INTERVAL_MINUTE(N)                 (((N)<<7)&0x1F80UL)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_INTERVAL_SECOND_MASK               (0x7EUL)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_INTERVAL_SECOND(N)                 (((N)<<1)&0x7EUL)
#define PMU_CTRL_RTC_CALIB_CTRL0_RTC_CALIB_TRIG_ENABLE                        (1<<0)


//MACROS of register rtc_calib_ctrl1
#define PMU_CTRL_RTC_CALIB_CTRL1_RTC_CALIB_OFFSET_MASK                        (0xFFFFUL)
#define PMU_CTRL_RTC_CALIB_CTRL1_RTC_CALIB_OFFSET(N)                          (((N)<<0)&0xFFFFUL)


//MACROS of register rtc_calib_status
#define PMU_CTRL_RTC_CALIB_STATUS_RTC_CALIB_DONE                              (1<<31)
#define PMU_CTRL_RTC_CALIB_STATUS_RTC_CALIB_VALUE_MASK                        (0x7FFFFFFUL)
#define PMU_CTRL_RTC_CALIB_STATUS_RTC_CALIB_VALUE(N)                          (((N)<<0)&0x7FFFFFFUL)


//MACROS of register wakeup_ctrl
#define PMU_CTRL_WAKEUP_CTRL_FREE_TIMER_WAKEUP_IRQ                            (1<<31)
#define PMU_CTRL_WAKEUP_CTRL_LPCOMP_WAKEUP_IRQ                                (1<<30)
#define PMU_CTRL_WAKEUP_CTRL_AONWDT_WAKEUP_IRQ                                (1<<29)
#define PMU_CTRL_WAKEUP_CTRL_AON_TIMER_WAKEUP_IRQ                             (1<<28)
#define PMU_CTRL_WAKEUP_CTRL_KEYPAD_WAKEUP_IRQ                                (1<<27)
#define PMU_CTRL_WAKEUP_CTRL_GPIO_WAKEUP_IRQ                                  (1<<26)
#define PMU_CTRL_WAKEUP_CTRL_RTC_WAKEUP_IRQ                                   (1<<25)
#define PMU_CTRL_WAKEUP_CTRL_BT_WAKEUP_IRQ                                    (1<<24)
#define PMU_CTRL_WAKEUP_CTRL_WAKEUP_IRQ_ENABLE_MASK                           (0xFF00UL)
#define PMU_CTRL_WAKEUP_CTRL_WAKEUP_IRQ_ENABLE(N)                             (((N)<<8)&0xFF00UL)
#define PMU_CTRL_WAKEUP_CTRL_FREE_TIMER_WAKEUP_MASK                           (1<<7)
#define PMU_CTRL_WAKEUP_CTRL_LPCOMP_WAKEUP_MASK                               (1<<6)
#define PMU_CTRL_WAKEUP_CTRL_AONWDT_WAKEUP_MASK                               (1<<5)
#define PMU_CTRL_WAKEUP_CTRL_AON_TIMER_WAKEUP_MASK                            (1<<4)
#define PMU_CTRL_WAKEUP_CTRL_KEYPAD_WAKEUP_MASK                               (1<<3)
#define PMU_CTRL_WAKEUP_CTRL_GPIO_WAKEUP_MASK                                 (1<<2)
#define PMU_CTRL_WAKEUP_CTRL_RTC_WAKEUP_MASK                                  (1<<1)
#define PMU_CTRL_WAKEUP_CTRL_BT_WAKEUP_MASK                                   (1<<0)


//MACROS of register wakeup_status
#define PMU_CTRL_WAKEUP_STATUS_FREE_TIMER_WAKEUP                              (1<<31)
#define PMU_CTRL_WAKEUP_STATUS_LPCOMP_WAKEUP                                  (1<<30)
#define PMU_CTRL_WAKEUP_STATUS_AONWDT_WAKEUP                                  (1<<29)
#define PMU_CTRL_WAKEUP_STATUS_AON_TIMER_WAKEUP                               (1<<28)
#define PMU_CTRL_WAKEUP_STATUS_KEYPAD_WAKEUP                                  (1<<27)
#define PMU_CTRL_WAKEUP_STATUS_GPIO_WAKEUP                                    (1<<26)
#define PMU_CTRL_WAKEUP_STATUS_RTC_WAKEUP                                     (1<<25)
#define PMU_CTRL_WAKEUP_STATUS_BT_WAKEUP                                      (1<<24)
#define PMU_CTRL_GPIOS_WAKEUP_STATUS_2_MASK                                   (0x300000UL)
#define PMU_CTRL_GPIOS_WAKEUP_STATUS_2(N)                                     (((N)<<20)&0x300000UL)
#define PMU_CTRL_GPIOS_WAKEUP_STATUS_MASK                                     (0x7FFFUL)
#define PMU_CTRL_GPIOS_WAKEUP_STATUS(N)                                       (((N)<<0)&0x7FFFUL)


//MACROS of register free_timer_cfg_0
#define PMU_CTRL_FREE_TIMER_CFG_0_FREE_TIMER_LOAD                             (1<<12)
#define PMU_CTRL_FREE_TIMER_CFG_0_FREE_TIMER_CAL_TIME_SEL_MASK                (0xF00UL)
#define PMU_CTRL_FREE_TIMER_CFG_0_FREE_TIMER_CAL_TIME_SEL(N)                  (((N)<<8)&0xF00UL)
#define PMU_CTRL_FREE_TIMER_CFG_0_FREE_TIMER_AUTO_CAL_TRIG_SEL_MASK           (0xF0UL)
#define PMU_CTRL_FREE_TIMER_CFG_0_FREE_TIMER_AUTO_CAL_TRIG_SEL(N)             (((N)<<4)&0xF0UL)
#define PMU_CTRL_FREE_TIMER_CFG_0_FREE_TIMER_CAL_TRIG                         (1<<3)
#define FREE_TIMER_CFG_0_FREE_TIMER_AUTO_CAL_TRIG_ENABLE                      (1<<2)
#define PMU_CTRL_FREE_TIMER_CFG_0_FREE_TIMER_CLEAR                            (1<<1)
#define PMU_CTRL_FREE_TIMER_CFG_0_FREE_TIMER_ENABLE                           (1<<0)


//MACROS of register free_timer_cfg_1
#define PMU_CTRL_FREE_TIMER_CFG_1_FREE_TIMER_LOAD_VALUE_MASK                  (0xFFFFFFFFUL)
#define PMU_CTRL_FREE_TIMER_CFG_1_FREE_TIMER_LOAD_VALUE(N)                    (((N)<<0)&0xFFFFFFFFUL)


//MACROS of register free_timer_cfg_2
#define PMU_CTRL_FREE_TIMER_CFG_2_FREE_TIMER_LOAD_VALUE_OFFSET_MASK           (0xFFFFUL)
#define PMU_CTRL_FREE_TIMER_CFG_2_FREE_TIMER_LOAD_VALUE_OFFSET(N)             (((N)<<0)&0xFFFFUL)


//MACROS of register free_timer_status
#define PMU_CTRL_FREE_TIMER_STATUS_FREE_TIMER_CNT_VALUE_MASK                  (0xFFFFFFFFUL)
#define PMU_CTRL_FREE_TIMER_STATUS_FREE_TIMER_CNT_VALUE(N)                    (((N)<<0)&0xFFFFFFFFUL)


//MACROS of register efuse_auto_rd
#define PMU_CTRL_EFUSE_AUTO_RD_EN                                             (1<<31)
#define PMU_CTRL_EFUSE_AUTO_RD_ST                                             (1<<30)
#define PMU_CTRL_EFUSE_AUTO_RD_EFUSE_CHIP_ID_WEN                              (1<<5)
#define PMU_CTRL_EFUSE_AUTO_RD_EFUSE_BOOT_MODE                                (1<<4)
#define PMU_CTRL_EFUSE_AUTO_RD_EFUSE_LDO_VSPI_VSEL                            (1<<2)
#define PMU_CTRL_EFUSE_AUTO_RD_EFUSE_XTAL_TYPE_MASK                           (0x3UL)
#define PMU_CTRL_EFUSE_AUTO_RD_EFUSE_XTAL_TYPE(N)                             (((N)<<0)&0x3UL)


//MACROS of register force_pm
#define PMU_CTRL_FORCE_PM_FORCE_SLEEP_CFG_EN                                  (1<<31)
#define PMU_CTRL_FORCE_PM_FORCE_SLEEP                                         (1<<0)


//MACROS of register cal_clk_ctrl
#define PMU_CTRL_CAL_CLK_CTRL_CAL_CLK_4M_DIV_MASK                             (0xF0UL)
#define PMU_CTRL_CAL_CLK_CTRL_CAL_CLK_4M_DIV(N)                               (((N)<<4)&0xF0UL)
#define PMU_CTRL_CAL_CLK_CTRL_CAL_CLK_4M_DIV_DR                               (1<<2)
#define PMU_CTRL_CAL_CLK_CTRL_CAL_CLK_4M_CFG_SET                              (1<<1)
#define PMU_CTRL_CAL_CLK_CTRL_CAL_CLK_4M_EN                                   (1<<0)


//MACROS of register pd_sys_frc_ctr2
#define PMU_CTRL_PD_SYS_FRC_CTR2_PD_MEM_GRP5_DR                               (1<<1)
#define PMU_CTRL_PD_SYS_FRC_CTR2_PD_MEM_GRP5_REG                              (1<<0)


//MACROS of register iomux_cfg6
#define PMU_CTRL_IOMUX_CFG6_GPIO21_IBIT_AON_MASK                              (0xC00000UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO21_IBIT_AON(N)                                (((N)<<22)&0xC00000UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO20_IBIT_AON_MASK                              (0x300000UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO20_IBIT_AON(N)                                (((N)<<20)&0x300000UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO_ANA_SEL3_MASK                                (0xF8000UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO_ANA_SEL3(N)                                  (((N)<<15)&0xF8000UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO_ANA_SEL2_MASK                                (0x7C00UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO_ANA_SEL2(N)                                  (((N)<<10)&0x7C00UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO_ANA_SEL1_MASK                                (0x3E0UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO_ANA_SEL1(N)                                  (((N)<<5)&0x3E0UL)
#define PMU_CTRL_IOMUX_CFG6_GPIO_ANA_SEL0_MASK                                (0x1FUL)
#define PMU_CTRL_IOMUX_CFG6_GPIO_ANA_SEL0(N)                                  (((N)<<0)&0x1FUL)


//MACROS of register pwr_base_cfg2
#define PMU_CTRL_PWR_BASE_CFG2_HIGHV_CHR_FINISH                               (1<<12)
#define PMU_CTRL_PWR_BASE_CFG2_HIGHV_LDO_CC_IBIT_MASK                         (0xF00UL)
#define PMU_CTRL_PWR_BASE_CFG2_HIGHV_LDO_CC_IBIT(N)                           (((N)<<8)&0xF00UL)
#define PMU_CTRL_PWR_BASE_CFG2_AC_ON                                          (1<<7)
#define PMU_CTRL_PWR_BASE_CFG2_HIGHV_ACON_DET_EN                              (1<<6)
#define PMU_CTRL_PWR_BASE_CFG2_HIGH_OUT_VBIT_MASK                             (0x3FUL)
#define PMU_CTRL_PWR_BASE_CFG2_HIGH_OUT_VBIT(N)                               (((N)<<0)&0x3FUL)


//MACROS of register kp_wakeup_ctrl
#define PMU_CTRL_KP_WAKEUP_CTRL_KP_WAKEUP_PIN_EN_2_MASK                       (0x300000UL)
#define PMU_CTRL_KP_WAKEUP_CTRL_KP_WAKEUP_PIN_EN_2(N)                         (((N)<<20)&0x300000UL)
#define PMU_CTRL_KP_WAKEUP_CTRL_KP_WAKEUP_PIN_EN_MASK                         (0x7FFFUL)
#define PMU_CTRL_KP_WAKEUP_CTRL_KP_WAKEUP_PIN_EN(N)                           (((N)<<0)&0x7FFFUL)



//pm_fsm_status, offset:0x0
typedef union
{
    u32 v;
    struct
    {
        u32  pm_fsm_state                            :4; /*[3:0], RO, 4'h0, */
        u32  da_ldo_vspi_en                          :1; /*[4], RO, 1'h0, readback value of DA_ldo_vspi_en*/
        u32  da_bg_en                                :1; /*[5], RO, 1'h0, readback value of DA_bg_en*/
        u32  da_xtal_en                              :1; /*[6], RO, 1'h0, readback value of DA_xtal_en*/
        u32  da_dcdc_ldo_en                          :1; /*[7], RO, 1'h0, readback value of DA_dcdc_ldo_en*/
        u32  pd_mem_grp0                             :1; /*[8], RO, 1'h0, ram0_0*/
        u32  pd_mem_grp1                             :1; /*[9], RO, 1'h0, ram0_1*/
        u32  pd_mem_grp2                             :1; /*[10], RO, 1'h0, ram1_0*/
        u32  pd_mem_grp3                             :1; /*[11], RO, 1'h0, ram1_1*/
        u32  pd_mem_grp4                             :1; /*[12], RO, 1'h0, ram1_2*/
        u32  pd_em0                                  :1; /*[13], RO, 1'h0, */
        u32  pd_em1                                  :1; /*[14], RO, 1'h0, */
        u32  pd_aon_sleep                            :1; /*[15], RO, 1'h0, */
        u32  vrtc_out_sel                            :1; /*[16], RO, 1'h0, */
        u32  rstb_dbb                                :1; /*[17], RO, 1'h0, */
        u32  xtal_ready                              :1; /*[18], RO, 1'h0, */
        u32  da_dcdc_buck_en                         :1; /*[19], RO, 1'h0, readback value of DA_dcdc_buck_en*/
        u32  pd_mem_grp5                             :1; /*[20], RO, 1'h0, ram4*/
        u32  reserved0                               :11; /*[31:21], RO, 11'h0, */
    }b;
}t_pmu_ctrl_pm_fsm_status;


//pwr_sys_ctrl, offset:0x4
typedef union
{
    u32 v;
    struct
    {
        u32  pm_reg                                  :2; /*[1:0], RW, 2'h0, power mode register
                                                          0:pm0
                                                          1:pm1
                                                          2:pm2
                                                          3:rfu*/
        u32  wait_xtal_ready_en                      :1; /*[2], RW, 1'h1, 1:wait xtal ready and then release dbb_reset*/
        u32  bor_reset_bypass                        :1; /*[3], RW, 1'h0, */
        u32  lowbat_off_bypass                       :1; /*[4], RW, 1'h0, 0: enter deep sleep mode when low battery status detected; 1: bypass the function.*/
        u32  ldo_vspi_en_dly                         :3; /*[7:5], RW, 3'h3, ldo_vspi power up delay after dcdc_ldo_en set. 2, 4, 5, 6, 7, 8, 10, 12 cycles of lpo32k (T). 0, 2T; 1, 4T; 2, 5T; 3, 6T; 4, 7T; 5, 8T; 6, 10T; 7, 12T.*/
        u32  clk_bt_sel                              :2; /*[9:8], RW, 2'h0, 0::lpo_clk
                                                          1::32k divided by xtal
                                                          2::32k xtal*/
        u32  reset_dly_time_sel                      :3; /*[12:10], RW, 3'h5, the intentional delay before releasing dbb reset. 0, 256T; 1, 2*256T; 2, 4*256T; 3, 8*256T; 4, 16*256T; 5, 25*256T; 6, 30*256T; 7, 50*256T.*/
        u32  xtal_rdy_time_sel                       :4; /*[16:13], RW, 4'ha, xtal ready delay time selection: 0, 1T; 1, 2T; 2, 4T; 3, 6T; 4, 8T; 5, 16T; 6, 25T; 7, 33T; 8, 49T; 9, 66T; 10, 82T; 11, 98T; 12, 131T; 13, 164T; 14, 197T; 15, 246T*/
        u32  dcdc_ldo_en_dly                         :2; /*[18:17], RW, 2'h1, DCDC_LDO power up delay in terms of 32k cycles(T) after BG_EN set. 0, 2T; 1, 4T; 2, 6T; 3, 8T?*/
        u32  clk_rtc_sel                             :2; /*[20:19], RW, 2'h0, 0::lpo_clk
                                                          1::32k divided by xtal
                                                          2::32k xtal*/
        u32  bg_en_dly                               :2; /*[22:21], RW, 2'h0, bandgap power up delay in terms of 32k cycles(T). 0, 2T; 1, 4T; 2, 6T; 3, 8T.*/
        u32  pd_interval_sel                         :2; /*[24:23], RW, 2'h1, power down interval select. 0, no delay among shutting down LDO_VSPI, DCDC_LDO and BG; 1, 1T interval; 2, 3T interval; 3, 5T interval.*/
        u32  reset_release_dly_en                    :1; /*[25], RW, 1'h0, 1:wait a delay time controlled by reset_dly_time_sel and then release dbb reset.*/
        u32  aonsleep_reset_bypass                   :1; /*[26], RW, 1'h0, 1:bypass resetn_dbb from aon_sleep*/
        u32  i2cs_disable                            :1; /*[27], RW, 1'h0, disable i2cs function of gpio8/9: 1, disable i2cs function; 0, enable i2cs function.*/
        u32  lowbat_det_en                           :1; /*[28], RW, 1'h1, low battery detection enable. High active.*/
        u32  vbat_monit_en                           :1; /*[29], RW, 1'h0, battery voltage monit function enable signal*/
        u32  i2cs_release                            :1; /*[30], RW, 1'h0, release gpio8/9's i2c function: 1, release gpio8/9 for all functions; 0, gpio8/9 as dedicated i2c slave scl/sda.*/
        u32  reserved0                               :1; /*[31], RO, 1'h0, */
    }b;
}t_pmu_ctrl_pwr_sys_ctrl;


//pm_fsm_ctrl, offset:0x8
typedef union
{
    u32 v;
    struct
    {
        u32  iref_local_en_reg                       :1; /*[0], RW, 1'h0, */
        u32  iref_local_en_dr                        :1; /*[1], RW, 1'h0, */
        u32  bg_en_reg                               :1; /*[2], RW, 1'h0, */
        u32  bg_en_dr                                :1; /*[3], RW, 1'h0, */
        u32  dcdc_ldo_en_reg                         :1; /*[4], RW, 1'h1, when dcdc_ldo_en_dr=1, DA_dcdc_ldo_en=dcdc_ldo_en_reg.*/
        u32  dcdc_ldo_en_dr                          :1; /*[5], RW, 1'h0, 1, DA_dcdc_ldo_en is from dcdc_ldo_en_reg; 0, from power state FSM*/
        u32  rstb_dbb_reg                            :1; /*[6], W1C, 1'h0, when rstb_dbb_dr set, writing 1 will reset main digital part.*/
        u32  rstb_dbb_dr                             :1; /*[7], RW, 1'h0, when set, enable rstb_dbb_reg's reset function for the main digital part.*/
        u32  pd_aon_sleep_reg                        :1; /*[8], RW, 1'h0, */
        u32  pd_aon_sleep_dr                         :1; /*[9], RW, 1'h0, */
        u32  pmu_ctrl_soft_resetn                    :1; /*[10], RW, 1'h1, reset the whole system, power up again*/
        u32  pmu_ctrl_soft_resetn_bypass             :1; /*[11], RW, 1'h1, */
        u32  vrtc_out_sel_reg                        :1; /*[12], RW, 1'h0, power switch for digital retention power to use vdig or vrtc. 0: select vrtc; 1: select vdig.*/
        u32  vrtc_out_sel_dr                         :1; /*[13], RW, 1'h0, */
        u32  dcdc_buck_en_reg                        :1; /*[14], RW, 1'h1, when dcdc_buck_en_dr=1, DA_dcdc_buck_en=dcdc_buck_en_reg.*/
        u32  dcdc_buck_en_dr                         :1; /*[15], RW, 1'h0, 1, DA_dcdc_buck_en is from dcdc_buck_en_reg; 0, from power state FSM*/
        u32  ldo_vdig_en_reg                         :1; /*[16], RW, 1'h1, when ldo_vdig_en_dr=1, DA_ldo_vdig_en=ldo_vdig_en_reg.*/
        u32  ldo_vdig_en_dr                          :1; /*[17], RW, 1'h0, 1, DA_ldo_vdig_en is from ldo_vdig_en_reg; 0, from power state FSM*/
        u32  reserved0                               :14; /*[31:18], RO, 14'h0, */
    }b;
}t_pmu_ctrl_pm_fsm_ctrl;


//xtal_clk32k_div, offset:0xc
typedef union
{
    u32 v;
    struct
    {
        u32  step_offset_lp                          :8; /*[7:0], RW, 8'h0, step offset value in low power mode.*/
        u32  step_offset_normal                      :8; /*[15:8], RW, 8'h0, step offset value in normal mode.*/
        u32  step_offset_update                      :1; /*[16], RW, 1'h0, clk32k_div compensation step offset update signal.*/
        u32  div_lp_mode_h                           :1; /*[17], RO, 1'h0, read back of div low power mode select, high active*/
        u32  div_lp_mode_h_reg                       :1; /*[18], RW, 1'h0, div low power mode select, high active*/
        u32  div_lp_mode_h_dr                        :1; /*[19], RW, 1'h0, 0: step_offset = step_offset_normal; 1, step_offset = step_offset_normal when div_lp_mode_h_reg=0, and step_offset = step_offset_lp when div_lp_mode_h_reg=1*/
        u32  clk32k_div_en                           :1; /*[20], RW, 1'h0, enable signal for clk32k_div clock, high active.*/
        u32  reserved0                               :10; /*[30:21], RO, 10'h0, */
        u32  xtal_lpn_en                             :1; /*[31], RW, 1'b0, xtal(main xtal) mode select signal: 0, low power mode; 1, low phase noise mode*/
    }b;
}t_pmu_ctrl_xtal_clk32k_div;


//xtal_cfg_ctrl0, offset:0x10
typedef union
{
    u32 v;
    struct
    {
        u32  xtal_en_reg                             :1; /*[0], RW, 1'h1, enable signal for xtal*/
        u32  xtal_en_dr                              :1; /*[1], RW, 1'h0, 1, DA_xtal_en is from Xtal_en_reg; 0, from FSM control*/
        u32  xtal_pwr_sel_reg                        :1; /*[2], RW, 1'h1, power source select signal, 0: from vcore;  1: from vrtc*/
        u32  xtal_pwr_sel_dr                         :1; /*[3], RW, 1'h0, 1, DA_xtal_pwr_sel is from Xtal_pwr_sel_reg; 0, from FSM control*/
        u32  xtal_ldo_vbit                           :3; /*[6:4], RW, 3'h4, xtal ldo output control bits:
                                                          000:  ~0.85V
                                                          011:  ~1.0V
                                                          110:  ~1.15V
                                                          111:  bypass*/
        u32  xtal_vamp_bit                           :4; /*[10:7], RW, 4'h8, oscillator dc bias current control bits*/
        u32  xtal_buf_drv_bit                        :3; /*[13:11], RW, 3'h0, oscillator output buffer drive ability control bits*/
        u32  xtal_fix_ibit                           :6; /*[19:14], RW, 6'h0, control bits of the fixed bias current which is added to oscillator*/
        u32  xtal_fixib_en                           :1; /*[20], RW, 1'h0, enable the fixed bias current for faster setting up*/
        u32  xtal_gm_boost_en                        :1; /*[21], RW, 1'h1, enable gm boost to save power*/
        u32  xtal_lp_mode_reg                        :1; /*[22], RW, 1'h1, enable adaptive bias working mode to save more power*/
        u32  xtal_lp_mode_dr                         :1; /*[23], RW, 1'h1, 1, DA_xtal_lp_mode is from Xtal_lp_mode_reg; 0, from FSM control*/
        u32  xtal_lp_mode_hw_en                      :1; /*[24], RW, 1'h1, enable bit for timer calibration in xtal low power mode.*/
        u32  xtal_cap_coarse                         :4; /*[28:25], RW, 4'h4, coarse tuning bits of load capacitance*/
        u32  xtal_doubler_en                         :1; /*[29], RW, 1'h1, clk to dig doubler enable*/
        u32  xtal_doubler_clk_edge_sel               :1; /*[30], RW, 1'h0, clk to dig sync edge sel, 0:positive; 1: negtive*/
        u32  xtal_doubler_delay_sel                  :1; /*[31], RW, 1'h0, doubler delay control. 0:for 12M xtal; 1:for 16M xtal*/
    }b;
}t_pmu_ctrl_xtal_cfg_ctrl0;


//xtal_cfg_ctrl1, offset:0x14
typedef union
{
    u32 v;
    struct
    {
        u32  xtal_cap_fine                           :6; /*[5:0], RW, 6'h10, fine tuning bits of load capacitance */
        u32  xtal_fix_ibit_xtal_type0                :6; /*[11:6], RW, 6'h0, xtal_fix_ibit values to apply when xtal_auto_cfg set and xtal_type ==00 in efuse auto read duration.*/
        u32  xtal_fix_ibit_xtal_type1                :6; /*[17:12], RW, 6'h0, xtal_fix_ibit values to apply when xtal_auto_cfg set and xtal_type ==01 in efuse auto read duration.*/
        u32  xtal_fix_ibit_xtal_type2                :6; /*[23:18], RW, 6'h0, xtal_fix_ibit values to apply when xtal_auto_cfg set and xtal_type ==10 in efuse auto read duration.*/
        u32  xtal_fix_ibit_xtal_type3                :6; /*[29:24], RW, 6'h0, xtal_fix_ibit values to apply when xtal_auto_cfg set and xtal_type ==11 in efuse auto read duration. */
        u32  xtal_auto_cfg                           :1; /*[30], RW, 1'h1, used to automatically set xtal_fix_ibit in different states with different xtal types.*/
        u32  xtal_clk2dig_en                         :1; /*[31], RW, 1'h1, clk for digital gate signal, 1: enable*/
    }b;
}t_pmu_ctrl_xtal_cfg_ctrl1;


//pwr_base_cfg, offset:0x18
typedef union
{
    u32 v;
    struct
    {
        u32  highv_ldo_discharge_en                  :1; /*[0], RW, 1'h0, enable discharging the output when power off, if not, ouput will be floating when disable the ldo*/
        u32  highv_ldo_antishoot_en                  :1; /*[1], RW, 1'h1, enable anti-over shooting from high load to light load*/
        u32  reserved0                               :3; /*[4:2], RO, 3'h0, */
        u32  highv_ldo_lpmode                        :2; /*[6:5], RW, 2'h0, highv ldo dc power cotrol bits*/
        u32  highv_ldo_hpmode                        :2; /*[8:7], RW, 2'h0, highv ldo dc power cotrol bits, set other values for better transient response*/
        u32  vbat_bor_en                             :1; /*[9], RW, 1'h1, enable vbat brown out reset*/
        u32  vbat_bor_vth                            :3; /*[12:10], RW, 3'h4, vbat brown out reset threshold control bits
                                                                         H->L(V)      L->H(V)
                                                             000       ~1.2            ~1.3
                                                             001       ~1.3            ~1.4
                                                             01*       ~1.4            ~1.5
                                                             1**       ~1.5            ~1.6*/
        u32  bypass_vrtc2vcore                       :1; /*[13], RW, 1'h0, enable signal for bypassing between vrtc and vcore when needed*/
        u32  vrtc_vbit                               :4; /*[17:14], RW, 4'hb, light load vrtc out put control bits:
                                                          0000:  ~0.8V
                                                          1000:  ~1.19V
                                                          1111:  ~1.5V*/
        u32  vrtc_decap_mode                         :1; /*[18], RW, 1'h0, vrtc output decap mode. 0: on chip; 1: offchip*/
        u32  vrtc_anti_overshoot_en                  :1; /*[19], RW, 1'h1, vrtc output anti overshooting function enable signal, can be disabled to save power under deepsleep mode*/
        u32  ldo_vdig_vbit                           :4; /*[23:20], RW, 4'hc, ldo for digital output tuning bits
                                                          from 0.8 to 1.15V, 25mV/step
                                                          bypass mode if vbit=1111*/
        u32  lowbat_vth_bit                          :2; /*[25:24], RW, 2'h3, low bat detect threshold voltage bits
                                                                    L->H         H->
                                                          00:     ~1.48V     ~1.4V
                                                          01:     ~1.58V     ~1.5V
                                                          10:     ~1.68V     ~1.6V
                                                          11:     ~1.78V     ~1.7V*/
        u32  iref_local_ptat_en                      :1; /*[26], RW, 1'h0, current reference block ptat mode enable*/
        u32  vrtc_vbit_lp                            :4; /*[30:27], RW, 4'hb, light load vrtc out put control bits in low power modes (PM1/PM2):
                                                          0000:  ~0.8V
                                                          1000:  ~1.19V
                                                          1111:  ~1.5V*/
        u32  vrtc_vbit_force                         :1; /*[31], RW, 1'h0, when set, only use vrtc_vbit for final DA_vrtc_vbit to control vrtc voltage. High active.*/
    }b;
}t_pmu_ctrl_pwr_base_cfg;


//buck_ctrl, offset:0x1c
typedef union
{
    u32 v;
    struct
    {
        u32  dcdc_buck_sel                           :1; /*[0], RW, 1'h0, dcdc buck select signal: 1, buck; 0, ldo.*/
        u32  dcdc_ldo_clmit_cc_sel                   :1; /*[1], RW, 1'h0, ldo current limit or current compensation mode sel, 0: clmit; 1:cc mode*/
        u32  dcdc_ldo_cc_en                          :1; /*[2], RW, 1'h1, ldo current compensation function enable signal*/
        u32  dcdc_softstart_en                       :1; /*[3], RW, 1'h0, dcdc buck mode, softstart function enable signal*/
        u32  dcdc_vout_bit                           :4; /*[7:4], RW, 4'h8, dcdc output voltage control bits, ~0.8V-~1.4V
                                                          */
        u32  dcdc_ldo_lpmode                         :1; /*[8], RW, 1'h0, ldo low power mode enable signal*/
        u32  dcdc_discharge_en                       :1; /*[9], RW, 1'h0, enable signal of discharging output  when turn off dcdc*/
        u32  dcdc_ldo_capless_en                     :1; /*[10], RW, 1'h1, capless mode enable signal, if ldo is configed to capless mode, DA_dcdc_ldo_cc_en should better be set to 0 after ldo setting up. */
        u32  reserved0                               :21; /*[31:11], RO, 21'h0, */
    }b;
}t_pmu_ctrl_buck_ctrl;


//ldo_vspi_ctrl, offset:0x20
typedef union
{
    u32 v;
    struct
    {
        u32  ldo_vspi_en_reg                         :1; /*[0], RW, 1'h1, ldo_vspi enable signal*/
        u32  ldo_vspi_clmit_cc_sel                   :1; /*[1], RW, 1'h0, ldo current limit or current compensation mode sel, 0: clmit; 1:cc mode*/
        u32  ldo_vspi_cc_en                          :1; /*[2], RW, 1'h1, ldo current compensation function enable signal*/
        u32  ldo_vspi_lpmode                         :1; /*[3], RW, 1'h0, ldo low power mode enable signal*/
        u32  ldo_vspi_vbit                           :3; /*[6:4], RW, 3'h4, ldo output control bits*/
        u32  vio_source_sel                          :1; /*[7], RW, 1'h1, gpios power source sel, 0: from ldo vspi; 1: from vbat*/
        u32  ldo_vio_ulp_antios_en                   :1; /*[8], RW, 1'h1, anti overshoot function for ultra low power ldo enable signal*/
        u32  ldo_vio_ulp_en                          :1; /*[9], RW, 1'h0, ultra low power ldo for gpio enable signal*/
        u32  viomux_en                               :1; /*[10], RW, 1'h1, enable for viomux output*/
        u32  ldo_vspi_vsel_reg                       :1; /*[11], RW, 1'h0, when efuse is not read out, DA_ldo_vspi_vsel will come from this register. ldo output range sel. 0: 1.8V; 1:2.5V
                                                          this signal comes from efuse or bonding option*/
        u32  ldo_vspi_capless_en                     :1; /*[12], RW, 1'h1, capless mode enable signal,  if ldo is configed to capless mode, DA_ldo_vspi_cc_en should better be set to 0 after ldo setting up. */
        u32  reserved0                               :19; /*[31:13], RO, 19'h0, */
    }b;
}t_pmu_ctrl_ldo_vspi_ctrl;


//ana_status, offset:0x24
typedef union
{
    u32 v;
    struct
    {
        u32  lowbat_det_out                          :1; /*[0], RO, 1'h0, battery voltage lower than uvlo threshold voltage set by uv_sel<1:0>. 
                                                          When it is ture, the system is not allowed to power on*/
        u32  bordet_out                              :1; /*[1], RO, 1'h1, brown out det out, active low*/
        u32  reserved0                               :30; /*[31:2], RO, 30'h0, */
    }b;
}t_pmu_ctrl_ana_status;


//pmu_ana_rsvd, offset:0x28
typedef union
{
    u32 v;
    struct
    {
        u32  da_pmu_reserved1                        :1;  /*[0], RW, use for vrtc_vbit_new[0]*/
        u32  da_pmu_reserved2                        :3;  /*[3:1], RW, used for charger chn selection.*/
        u32  da_pmu_reserved3                        :8;  /*[11:4], RW, 16'h5555, reserved for future pmu ana use*/
        u32  da_pmu_reserved4                        :2;  /*[13:12], RW, used for vcore calibration*/
        u32  da_pmu_reserved5                        :2;  /*[15:14], RW, 16'h5555, reserved for future pmu ana use*/
        u32  ad_pmu_reserved                         :8;  /*[23:16], RO, 8'h0, reserved for future pmu ana use*/
        u32  reserved0                               :8;  /*[31:24], RO, 8'h0, */
    }b;
}t_pmu_ctrl_pmu_ana_rsvd;


//sw_rsvd, offset:0x2c
typedef union
{
    u32 v;
    struct
    {
        u32  gpadc_calib_type                        :1; /*[0], RW, 1'h0, software use.*/
		u32  shutdown								 :1; /*[1], RW, 1'h0, 1:shutdown system by user.'*/
        u32  rsvd_for_future                         :6; /*[7:2], RW, 6'h0, */
        u32  reserved0                               :24; /*[31:8], RO, 24'h0, */
    }b;
}t_pmu_ctrl_sw_rsvd;


//misc_ctrl, offset:0x30
typedef union
{
    u32 v;
    struct
    {
        u32  div_cnt_disable                         :1; /*[0], RW, 1'h0, rtc calendar div counter disable.*/
        u32  en_kp_gating_clk                        :1; /*[1], RW, 1'h0, gating lpo32k clock when entering sleep modes. High active.*/
        u32  xtal_type_reg                           :2; /*[3:2], RW, 2'h0, The value is used for xtal_type before efuse's first reading.
                                                          2'h0: Xtal32Mhz, 
                                                          2'h1:Xtal24Mhz, 
                                                          2'h2: Xtal16Mhz, 
                                                          2'h3: Xtal 12Mhz*/
        u32  em_ds_reg                               :2; /*[5:4], RW, 2'h0, em's ds configure, [1]em1, [0]em0*/
        u32  em_ls_reg                               :2; /*[7:6], RW, 2'h0, em's ls configure, [1]em1, [0]em0*/
        u32  ram_ds_reg                              :6; /*[13:8], RW, 6'h0, [5], ds(RET) for ram4; [4], ds(RET) for ram1_2; [3], ds(RET) for ram1_1; [2], ds(RET) for ram1_0; [1], ds(RET) for ram0_1; [0], ds(RET) for ram0_0*/
        u32  ram_ls_reg                              :6; /*[19:14], RW, 6'h0, [5], ls(NAP) for ram4; [4], ls(NAP) for ram1_2; [3], ls(NAP) for ram1_1; [2], ls(NAP) for ram1_0; [1], ls(NAP) for ram0_1; [0], ls(NAP) for ram0_0*/
        u32  ram_ls_ds_dr                            :6; /*[25:20], RW, 6'h0, if ram_ls_ds_dr=1, corresponding ram0_0/ram0_1/ram1_0/ram1_1/ram1_2/ram4's ls(NAP) and ds(RET) are from ram_ls_reg and ram_ds_reg separately. [5], ram4; [4], ram1_2; [3], ram1_1; [2], ram1_0; [1], ram0_1; [0], ram0_0*/
        u32  pm0_pd_xtal                             :1; /*[26], RW, 1'h0, manually shut down xtal in PM0 state. High active.*/
        u32  clk_ir_sel                              :2; /*[28:27], RW, 2'h1, 0::lpo_clk
                                                          1::xtal_div_32k
                                                          2::xtal_clk32k*/
        u32  boot_mode_reg                           :1; /*[29], RW, 1'h1, The value is used for boot_mode before efuse's first reading. 0, boot from rom; 1, boot from flash.*/
        u32  boot_mode_force                         :1; /*[30], RW, 1'h1, when set, use boot_mode_reg as final boot_mode value and ignoring the related boot_mode value from efuse.*/
        u32  reserved0                               :1; /*[31], RO, 1'h0, */
    }b;
}t_pmu_ctrl_misc_ctrl;


//sys_ctrl_protect, offset:0x34
typedef union
{
    u32 v;
    struct
    {
        u32  sys_ctrl_lock                           :1; /*[0], RWE, 1'h0, write 0x524d4321 to set lock
                                                          write 0x524d1234 to release lock*/
        u32  reserved0                               :31; /*[31:1], RO, 31'h0, */
    }b;
}t_pmu_ctrl_sys_ctrl_protect;


//pmu_ctrl_protect, offset:0x38
typedef union
{
    u32 v;
    struct
    {
        u32  pmu_ctrl_lock                           :1; /*[0], RWE, 1'h0, write 0x524d8765 to set lock
                                                          write 0x524d5678 to release lock*/
        u32  reserved0                               :31; /*[31:1], RO, 31'h0, */
    }b;
}t_pmu_ctrl_protect;


//pd_sys_frc_ctr, offset:0x3c
typedef union
{
    u32 v;
    struct
    {
        u32  pd_mem_grp0_reg                         :1; /*[0], RW, 1'h0, sram 8kb(ram0_0) power down control: 1, power down; 0, power on*/
        u32  pd_mem_grp0_dr                          :1; /*[1], RW, 1'h0, directly use pd_mem_grp0_reg to power down ram0_0.*/
        u32  pd_mem_grp1_reg                         :1; /*[2], RW, 1'h0, sram 8kb(ram0_1) power down control: 1, power down; 0, power on*/
        u32  pd_mem_grp1_dr                          :1; /*[3], RW, 1'h0, directly use pd_mem_grp1_reg to power down ram0_1.*/
        u32  pd_mem_grp2_reg                         :1; /*[4], RW, 1'h0, sram 8kb(ram1_0)  power down control: 1, power down; 0, power on*/
        u32  pd_mem_grp2_dr                          :1; /*[5], RW, 1'h0, directly use pd_mem_grp2_reg to power down ram1_0.*/
        u32  pd_mem_grp3_reg                         :1; /*[6], RW, 1'h0, sram 4kb unit0(ram1_1)  power down control: 1, power down; 0, power on*/
        u32  pd_mem_grp3_dr                          :1; /*[7], RW, 1'h0, directly use pd_mem_grp3_reg to power down ram1_1.*/
        u32  pd_mem_grp4_reg                         :1; /*[8], RW, 1'h0, sram 4kb unit1(ram1_2) power down control: 1, power down; 0, power on*/
        u32  pd_mem_grp4_dr                          :1; /*[9], RW, 1'h0, directly use pd_mem_grp4_reg to power down ram1_2.*/
        u32  pd_em0_reg                              :1; /*[10], RW, 1'h0, 1, power down; 0, power on*/
        u32  pd_em0_dr                               :1; /*[11], RW, 1'h0, directly use pd_em0_reg to power down em0.*/
        u32  pd_em1_reg                              :1; /*[12], RW, 1'h0, 1, power down; 0, power on*/
        u32  pd_em1_dr                               :1; /*[13], RW, 1'h0, directly use pd_em1_reg to power down em1.*/
        u32  mem_grp0_on                             :1; /*[14], RW, 1'h1, keep mem grp0 on in pm1/pm2 modes, high active*/
        u32  mem_grp1_on                             :1; /*[15], RW, 1'h1, keep mem grp1 on in pm1/pm2 modes, high active*/
        u32  mem_grp2_on                             :1; /*[16], RW, 1'h1, keep mem grp2 on in pm1/pm2 modes, high active*/
        u32  mem_grp3_on                             :1; /*[17], RW, 1'h1, keep mem grp3 on in pm1/pm2 modes, high active*/
        u32  mem_grp4_on                             :1; /*[18], RW, 1'h1, keep mem grp4 on in pm1/pm2 modes, high active*/
        u32  em0_on                                  :1; /*[19], RW, 1'h1, keep em 4k #0 on in pm1/pm2 modes, high active*/
        u32  em1_on                                  :1; /*[20], RW, 1'h1, keep em 4k #1 on in pm1/pm2 modes, high active*/
        u32  mem_ls_mode                             :1; /*[21], RW, 1'h0, control active cpu srams in normal state to enter ls(NAP) mode in low power modes, high active.*/
        u32  mem_ds_mode                             :1; /*[22], RW, 1'h0, control active cpu srams in normal state to enter ds(RET) mode in low power modes, high active. To get this, for M31 memory, also need to set mem_ls_mode = 1 before entering low power modes.*/
        u32  em0_iso                                 :1; /*[23], RW, 1'h0, set this bit if you need to keep em on in PM2 state*/
        u32  em1_iso                                 :1; /*[24], RW, 1'h0, set this bit if you need to keep em on in PM2 state*/
        u32  pd_mcu_vddg_reg                         :1; /*[25], RW, 1'h0, 1, power down; 0, power on*/
        u32  pd_mcu_vddg_dr                          :1; /*[26], RW, 1'h0, directly use pd_mcu_vddg_reg to power down mcu_vddg.*/
        u32  pd_btrf_vddg_reg                        :1; /*[27], RW, 1'h0, 1, power down; 0, power on*/
        u32  pd_btrf_vddg_dr                         :1; /*[28], RW, 1'h0, directly use pd_btrf_vddg_reg to power down btrf_vddg.*/
        u32  mcu_retention_en                        :1; /*[29], RW, 1'h0, if enter PM2, pls set it to 0.*/
        u32  rf_retention_en                         :1; /*[30], RW, 1'h0, if enter PM2, pls set it to 0.*/
        u32  mem_grp5_on                             :1; /*[31], RW, 1'h1, keep mem grp5 on in pm1/pm2 modes, high active*/
    }b;
}t_pmu_ctrl_pd_sys_frc_ctr;


//iomux_cfg0, offset:0x40
typedef union
{
    u32 v;
    struct
    {
        u32  gpio_wakeup_polarity                    :15; /*[14:0], RW, 15'h7fff, [14:0] for gpio14~gpio0. 0, low level wakeup; 1, high level wakeup.*/
        u32  reserved2                               :5; /*[19:15], RO, 5'h0, */
        u32  gpio_wakeup_polarity_2                  :2; /*[21:20], RW, 2'h3, [1:0] for gpio21~gpio20. 0, low level wakeup; 1, high level wakeup.*/
        u32  reserved1                               :3; /*[24:22], RO, 3'h0, */
        u32  kp_wakeup_sel                           :1; /*[25], RW, 1'h0, 0: gpio0~4 and gpio14,21 drive, gpio5~13, 20 wakeup; 1, gpio5~10 drive, gpio0~4 and gpio11~14, 20~21 wakeup*/
        u32  kp_in_polarity                          :1; /*[26], RW, 1'h0, indicate key pad input polarity in low power modes.*/
        u32  kp_out_polarity                         :1; /*[27], RW, 1'h0, indicate key pad output polarity in low power modes.*/
        u32  reserved0                               :4; /*[31:28], RO, 4'h0, */
    }b;
}t_pmu_ctrl_iomux_cfg0;


//iomux_cfg1, offset:0x44
typedef union
{
    u32 v;
    struct
    {
        u32  gpio0_func_sel                          :1; /*[0], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio1_func_sel                          :1; /*[1], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio2_func_sel                          :2; /*[3:2], RW, 2'h0, gpio2
                                                          0: gpio
                                                          1: gpio_wakeup
                                                          2: hci_wakeup
                                                          3: reserved*/
        u32  gpio3_func_sel                          :2; /*[5:4], RW, 2'h0, gpio3
                                                          0: gpio
                                                          1: gpio_wakeup
                                                          2: hci_wakeup
                                                          3: reserved*/
        u32  gpio4_func_sel                          :2; /*[7:6], RW, 2'h0, gpio4
                                                          0: gpio
                                                          1: gpio_wakeup
                                                          2: aon_pwm
                                                          3: reserved*/
        u32  gpio5_func_sel                          :1; /*[8], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio6_func_sel                          :1; /*[9], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio7_func_sel                          :1; /*[10], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio8_func_sel                          :1; /*[11], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio9_func_sel                          :2; /*[13:12], RW, 2'h0, 0: gpio, 1: gpio_wakeup, 2: aon_pwm
                                                          3: reserved*/
        u32  gpio10_func_sel                         :1; /*[14], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio11_func_sel                         :1; /*[15], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio12_func_sel                         :1; /*[16], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio13_func_sel                         :1; /*[17], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio14_func_sel                         :1; /*[18], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio20_func_sel                         :1; /*[19], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  gpio21_func_sel                         :1; /*[20], RW, 1'h0, 0: gpio, 1: gpio_wakeup*/
        u32  reserved0                               :11; /*[31:21], RO, 11'h0, */
    }b;
}t_pmu_ctrl_iomux_cfg1;


//iomux_cfg2, offset:0x48
typedef union
{
    u32 v;
    struct
    {
        u32  pdn_gpio_aon                            :15; /*[14:0], RW, 15'h7FFF, [14:0] for gpio0~gpio14. 0, power down; 1, power up.*/
        u32  reserved1                               :5; /*[19:15], RO, 5'h0, */
        u32  pdn_gpio_aon_2                          :2; /*[21:20], RW, 2'h3, [1:0] for gpio21~gpio20. 0, power down; 1, power up.*/
        u32  reserved0                               :10; /*[31:22], RO, 10'h0, */
    }b;
}t_pmu_ctrl_iomux_cfg2;


//iomux_cfg3, offset:0x4c
typedef union
{
    u32 v;
    struct
    {
        u32  pullup_gpio_aon                         :15; /*[14:0], RW, 15'h0, [14:0] for gpio0~gpio14. 0, no pullup; 1, pullup.*/
        u32  reserved1                               :5; /*[19:15], RO, 5'h0, */
        u32  pullup_gpio_aon_2                       :2; /*[21:20], RW, 2'h0, [1:0] for gpio21~gpio20. 0, no pullup; 1, pullup.*/
        u32  reserved0                               :10; /*[31:22], RO, 10'h0, */
    }b;
}t_pmu_ctrl_iomux_cfg3;


//iomux_cfg4, offset:0x50
typedef union
{
    u32 v;
    struct
    {
        u32  pulldn_gpio_aon                         :15; /*[14:0], RW, 15'h0, [14:0] for gpio0~gpio14. 0, no pulldown; 1, pulldown.*/
        u32  reserved1                               :5; /*[19:15], RO, 5'h0, */
        u32  pulldn_gpio_aon_2                       :2; /*[21:20], RW, 2'h0, [1:0] for gpio21~gpio20. 0, no pulldown; 1, pulldown.*/
        u32  reserved0                               :10; /*[31:22], RO, 10'h0, */
    }b;
}t_pmu_ctrl_iomux_cfg4;


//iomux_cfg5, offset:0x54
typedef union
{
    u32 v;
    struct
    {
        u32  gpio0_ibit_aon                          :2; /*[1:0], RW, 2'h2, */
        u32  gpio1_ibit_aon                          :2; /*[3:2], RW, 2'h2, */
        u32  gpio2_ibit_aon                          :2; /*[5:4], RW, 2'h2, */
        u32  gpio3_ibit_aon                          :2; /*[7:6], RW, 2'h2, */
        u32  gpio4_ibit_aon                          :2; /*[9:8], RW, 2'h2, */
        u32  gpio5_ibit_aon                          :2; /*[11:10], RW, 2'h2, */
        u32  gpio6_ibit_aon                          :2; /*[13:12], RW, 2'h2, */
        u32  gpio7_ibit_aon                          :2; /*[15:14], RW, 2'h2, */
        u32  gpio8_ibit_aon                          :2; /*[17:16], RW, 2'h2, */
        u32  gpio9_ibit_aon                          :2; /*[19:18], RW, 2'h2, */
        u32  gpio10_ibit_aon                         :2; /*[21:20], RW, 2'h2, */
        u32  gpio11_ibit_aon                         :2; /*[23:22], RW, 2'h2, */
        u32  gpio12_ibit_aon                         :2; /*[25:24], RW, 2'h2, */
        u32  gpio13_ibit_aon                         :2; /*[27:26], RW, 2'h2, */
        u32  gpio14_ibit_aon                         :2; /*[29:28], RW, 2'h2, */
        u32  reserved0                               :2; /*[31:30], RO, 2'h0, */
    }b;
}t_pmu_ctrl_iomux_cfg5;


//lpcomp_ctrl, offset:0x58
typedef union
{
    u32 v;
    struct
    {
        u32  lpcomp_vref_sel                         :5; /*[4:0], RW, 5'h10, lpcomp reference level select: 0, external reference, 1~31, different internal reference level.*/
        u32  lpcomp_ch_sel                           :3; /*[7:5], RW, 3'h0, lpcomp analog input mux selection*/
        u32  lpcomp_reset                            :1; /*[8], RW, 1'h0, low power comparator output reset signal*/
        u32  lpcomp_en                               :1; /*[9], RW, 1'h0, lpcomp power up*/
        u32  lpcomp_wakeup_mode                      :2; /*[11:10], RW, 2'h0, 0: posedge or negedge; 1, posedge; 2/3, negedge*/
        u32  lpcomp_out                              :1; /*[12], RO, 1'h0, */
        u32  reserved0                               :19; /*[31:13], RO, 19'h0, */
    }b;
}t_pmu_ctrl_lpcomp_ctrl;


//lpo32k_xtal32k_ctrl, offset:0x5c
typedef union
{
    u32 v;
    struct
    {
        u32  lpo32k_en_reg                           :1; /*[0], RW, 1'h1, enable signal for lpo32k, default should be high after por. This bit needs to be 0 when you want to shut down lpo32k in sleep mode.*/
        u32  lpo32k_ldo_en                           :1; /*[1], RW, 1'h0, ldo for lpo32k enable signal, if not enable, lpo32k work under vrtc.*/
        u32  lpo32k_ldo_vbit                         :2; /*[3:2], RW, 2'h3, ldo for lpo32k output control bits
                                                          00: ~625mV
                                                          01:~650mV
                                                          10:~675mV
                                                          11:~700mV*/
        u32  lpo32k_rbit                             :5; /*[8:4], RW, 5'h10, lpo32k RC value control bits, frequency is inversely proportional to its value*/
        u32  xtal32k_en                              :1; /*[9], RW, 1'h0, enable singal for xtal32k*/
        u32  xtal32k_ibias_bit                       :3; /*[12:10], RW, 3'h4, dc bias current control bits*/
        u32  xtal32k_cbit                            :5; /*[17:13], RW, 5'h18, load capacitance tuning bits, default about 12.5pF*/
        u32  reserved0                               :14; /*[31:18], RO, 14'h0, */
    }b;
}t_pmu_ctrl_lpo32k_xtal32k_ctrl;


//rtc_calib_ctrl0, offset:0x60
typedef union
{
    u32 v;
    struct
    {
        u32  rtc_calib_trig_enable                   :1; /*[0], RW, 1'h0, */
        u32  rtc_calib_interval_second               :6; /*[6:1], RW, 6'ha, (rtc_calib_interval_second+1) second*/
        u32  rtc_calib_interval_minute               :6; /*[12:7], RW, 6'h0, (rtc_calib_interval_minute +1) minutes*/
        u32  rtc_calib_interval_hour                 :5; /*[17:13], RW, 5'h0, (rtc_calib_interval_hour +1) hours*/
        u32  rtc_calib_time_sel                      :4; /*[21:18], RW, 4'h0, Calibration time selection.
                                                          RTC calibration time is 2^(1+rtc_calib_time_sel) RC clock cycle.*/
        u32  rtc_calib_trig_mode                     :1; /*[22], RW, 1'h0, 0:: trig_at_once trigger calibration once the enable set 
                                                          1:: trig_interval trigger calibtation after interval*/
        u32  rtc_calib_clk_sel                       :1; /*[23], RW, 1'h0, RTC calibration clock select
                                                          0:: Calibrate using 4MHz clock
                                                          1:: Calibrate using xtal lp clock*/
        u32  reserved1                               :6; /*[29:24], RO, 6'h0, */
        u32  rtc_calib_switch_mode                   :1; /*[30], RW, 1'h0, 0:: mode0
                                                          Switch at once
                                                          1:: mode1
                                                          Swith at one second event*/
        u32  reserved0                               :1; /*[31], RO, 1'h0, */
    }b;
}t_pmu_ctrl_rtc_calib_ctrl0;


//rtc_calib_ctrl1, offset:0x64
typedef union
{
    u32 v;
    struct
    {
        u32  rtc_calib_offset                        :16; /*[15:0], RW, 16'h0, signed offset, range from  - 32768 to 32767*/
        u32  reserved0                               :16; /*[31:16], RO, 16'h0, */
    }b;
}t_pmu_ctrl_rtc_calib_ctrl1;


//rtc_calib_status, offset:0x68
typedef union
{
    u32 v;
    struct
    {
        u32  rtc_calib_value                         :27; /*[26:0], RO, 27'h0, Current calibration Value*/
        u32  reserved0                               :4; /*[30:27], RO, 4'h0, */
        u32  rtc_calib_done                          :1; /*[31], RO, 1'h0, RTC calibration done*/
    }b;
}t_pmu_ctrl_rtc_calib_status;


//wakeup_ctrl, offset:0x6c
typedef union
{
    u32 v;
    struct
    {
        u32  bt_wakeup_mask                          :1; /*[0], RW, 1'h0, */
        u32  rtc_wakeup_mask                         :1; /*[1], RW, 1'h1, */
        u32  gpio_wakeup_mask                        :1; /*[2], RW, 1'h1, */
        u32  keypad_wakeup_mask                      :1; /*[3], RW, 1'h0, */
        u32  aon_timer_wakeup_mask                   :1; /*[4], RW, 1'h1, */
        u32  aonwdt_wakeup_mask                      :1; /*[5], RW, 1'h1, */
        u32  lpcomp_wakeup_mask                      :1; /*[6], RW, 1'h0, */
        u32  free_timer_wakeup_mask                  :1; /*[7], RW, 1'h0, mask the wake-up sources: 0, mask;1, unmask*/
        u32  wakeup_irq_enable                       :8; /*[15:8], RW, 8'h0, [15:8] as list [7:0]
                                                          wake up irq enable, different from wakeup_mask below. Irq_enable is used to enable interrupts generated by wakeup, while wakeup_mask is used to enable wakeup the pmu state. Wakeup_mask may be used, but irq may be not enable. And to get interrupt when waking up, you must set the related wakeup_mask to 1 in advance.*/
        u32  reserved0                               :8; /*[23:16], RO, 8'h0, */
        u32  bt_wakeup_irq                           :1; /*[24], RO, 1'h0, */
        u32  rtc_wakeup_irq                          :1; /*[25], RO, 1'h0, */
        u32  gpio_wakeup_irq                         :1; /*[26], RO, 1'h0, */
        u32  keypad_wakeup_irq                       :1; /*[27], RO, 1'h0, */
        u32  aon_timer_wakeup_irq                    :1; /*[28], RO, 1'h0, */
        u32  aonwdt_wakeup_irq                       :1; /*[29], RO, 1'h0, */
        u32  lpcomp_wakeup_irq                       :1; /*[30], RO, 1'h0, */
        u32  free_timer_wakeup_irq                   :1; /*[31], RO, 1'h0, wakeup interrupt status after combining wakeup_mask in always-on domain: high active*/
    }b;
}t_pmu_ctrl_wakeup_ctrl;


//wakeup_status, offset:0x70
typedef union
{
    u32 v;
    struct
    {
        u32  gpios_wakeup_status                     :15; /*[14:0], RO, 15'h0, gpio wakeup status after combining wakeup_mask : high active*/
        u32  reserved1                               :5; /*[19:15], RO, 5'h0, */
        u32  gpios_wakeup_status_2                   :2; /*[21:20], RO, 2'h0, [1] and [0] for gpio21 and gpio20 separately. gpio wakeup status after combining wakeup_mask : high active*/
        u32  reserved0                               :2; /*[23:22], RO, 2'h0, */
        u32  bt_wakeup                               :1; /*[24], RO, 1'h0, */
        u32  rtc_wakeup                              :1; /*[25], RO, 1'h0, */
        u32  gpio_wakeup                             :1; /*[26], RO, 1'h0, */
        u32  keypad_wakeup                           :1; /*[27], RO, 1'h0, */
        u32  aon_timer_wakeup                        :1; /*[28], RO, 1'h0, */
        u32  aonwdt_wakeup                           :1; /*[29], RO, 1'h0, */
        u32  lpcomp_wakeup                           :1; /*[30], RO, 1'h0, */
        u32  free_timer_wakeup                       :1; /*[31], RO, 1'h0, direct wakeup status to power state after combining wakeup_mask : high active*/
    }b;
}t_pmu_ctrl_wakeup_status;


//free_timer_cfg_0, offset:0x74
typedef union
{
    u32 v;
    struct
    {
        u32  free_timer_enable                       :1; /*[0], RW, 1'h0, */
        u32  free_timer_clear                        :1; /*[1], W1C, 1'h0, */
        u32  free_timer_auto_cal_trig_enable         :1; /*[2], RW, 1'h0, enable automatically calibration trigger*/
        u32  free_timer_cal_trig                     :1; /*[3], W1S, 1'h0, software trigger*/
        u32  free_timer_auto_cal_trig_sel            :4; /*[7:4], RW, 4'h0, automaticallycalibration tirgger every 
                                                          2^(6+trig_sel) rc clock cycles, bit[7] is not used.*/
        u32  free_timer_cal_time_sel                 :4; /*[11:8], RW, 4'h0, calibration time = 2^cali_timer_sel* Trc_clk*/
        u32  free_timer_load                         :1; /*[12], W1S, 1'h0, */
        u32  reserved0                               :19; /*[31:13], RO, 19'h0, */
    }b;
}t_pmu_ctrl_free_timer_cfg_0;


//free_timer_cfg_1, offset:0x78
typedef union
{
    u32 v;
    struct
    {
        u32  free_timer_load_value                   :32; /*[31:0], RW, 32'h100, */
    }b;
}t_pmu_ctrl_free_timer_cfg_1;


//free_timer_cfg_2, offset:0x7c
typedef union
{
    u32 v;
    struct
    {
        u32  free_timer_load_value_offset            :16; /*[15:0], RW, 16'h0, 16-bit signed number. use it to compensate rtc clock change beyond calibration.*/
        u32  reserved0                               :16; /*[31:16], RO, 16'h0, */
    }b;
}t_pmu_ctrl_free_timer_cfg_2;


//free_timer_status, offset:0x80
typedef union
{
    u32 v;
    struct
    {
        u32  free_timer_cnt_value                    :32; /*[31:0], RO, 32'h0, */
    }b;
}t_pmu_ctrl_free_timer_status;


//efuse_auto_rd, offset:0x84
typedef union
{
    u32 v;
    struct
    {
        u32  efuse_xtal_type                         :2; /*[1:0], RO, 2'h0, 2'h0: Xtal32Mhz, 
                                                          2'h1:Xtal24Mhz, 
                                                          2'h2: Xtal16Mhz, 
                                                          2'h3: Xtal12Mhz*/
        u32  efuse_ldo_vspi_vsel                     :1; /*[2], RO, 1'h0, when efuse is read out, DA_ldo_vspi_vsel will come from this register. ldo output range sel. 0: 1.8V; 1:2.5V
                                                          this signal comes from efuse or bonding option*/
        u32  reserved1                               :1; /*[3], RO, 1'h0, */
        u32  efuse_boot_mode                         :1; /*[4], RO, 1'h0, 0, rom; 1, flash.*/
        u32  efuse_chip_id_wen                       :1; /*[5], RO, 1'h0, 0, allow chip id programming; 1, forbid chip id programming*/
        u32  reserved0                               :24; /*[29:6], RO, 24'h0, */
        u32  efuse_auto_rd_st                        :1; /*[30], RO, 1'h0, The flag is used to indicate if the fuse has been read out once.1, been read; 0, not read.*/
        u32  efuse_auto_rd_en                        :1; /*[31], RW, 1'h0, */
    }b;
}t_pmu_ctrl_efuse_auto_rd;


//force_pm, offset:0x88
typedef union
{
    u32 v;
    struct
    {
        u32  force_sleep                             :1; /*[0], W1S, 1'h0, force PM state into specific pm as listed in pm_reg*/
        u32  reserved0                               :30; /*[30:1], RO, 30'h0, */
        u32  force_sleep_cfg_en                      :1; /*[31], RW, 1'h0, */
    }b;
}t_pmu_ctrl_force_pm;


//cal_clk_ctrl, offset:0x8c
typedef union
{
    u32 v;
    struct
    {
        u32  cal_clk_4m_en                           :1; /*[0], RW, 1'h0, calibrating clock enable, high active*/
        u32  cal_clk_4m_cfg_set                      :1; /*[1], RW, 1'h0, config signal for divider ratio of cal clock 4m. Need to set it to 1 first and then clear it to 0.*/
        u32  cal_clk_4m_div_dr                       :1; /*[2], RW, 1'h0, when this bit is set, the divider ratio from xtal clock to generate cal clock 4m is up to cal_clk_4m_div_reg. Otherwise, the divider ratio will be deduced by xtal_type automatically.*/
        u32  reserved1                               :1; /*[3], RO, 1'h0, */
        u32  cal_clk_4m_div                          :4; /*[7:4], RW, 4'h8, divider ratio to generate cal clock 4m from xtal clock */
        u32  reserved0                               :24; /*[31:8], RO, 24'h0, */
    }b;
}t_pmu_ctrl_cal_clk_ctrl;


//pd_sys_frc_ctr2, offset:0x90
typedef union
{
    u32 v;
    struct
    {
        u32  pd_mem_grp5_reg                         :1; /*[0], RW, 1'h0, ram4(8KB) power down control: 1, power down; 0, power on*/
        u32  pd_mem_grp5_dr                          :1; /*[1], RW, 1'h0, directly use pd_mem_grp5_reg to power down ram0_0.*/
        u32  reserved0                               :30; /*[31:2], RO, 30'h0, */
    }b;
}t_pmu_ctrl_pd_sys_frc_ctr2;


//iomux_cfg6, offset:0x94
typedef union
{
    u32 v;
    struct
    {
        u32  gpio_ana_sel0                           :5; /*[4:0], RW, 5'h0, [4:0] for gpio14~10, analog function 0 selection. Currently, [4:3] for xtal32k, [2:0] reserved.*/
        u32  gpio_ana_sel1                           :5; /*[9:5], RW, 5'h0, [4:0]for gpio14~10, analog function 1 selection, i.e. test function. high active. Should be cleared to 0s before entering sleep modes.*/
        u32  gpio_ana_sel2                           :5; /*[14:10], RW, 5'h0, [4:0]for gpio14~10, analog function 2 selection, i.e. gpadc function. high active. Should be cleared to 0s before entering sleep modes.*/
        u32  gpio_ana_sel3                           :5; /*[19:15], RW, 5'h0, [4:0]for gpio14~10, analog function 3 selection, i.e. lpcomp function. high active.*/
        u32  gpio20_ibit_aon                         :2; /*[21:20], RW, 2'h2, */
        u32  gpio21_ibit_aon                         :2; /*[23:22], RW, 2'h2, */
        u32  reserved0                               :8; /*[31:24], RO, 8'h0, */
    }b;
}t_pmu_ctrl_iomux_cfg6;


//pwr_base_cfg2, offset:0x98
typedef union
{
    u32 v;
    struct
    {
        u32  high_out_vbit                           :6; /*[5:0], RW, 6'h0, highv ldo output control bit, 64 steps; when use as charger, bit<5>should set 1, and the other bits come from efuse which save the trimming data.
                                                          00000:   ~3.3V
                                                          10000:   ~3.8V
                                                          11111:   ~4.5V*/
        u32  highv_acon_det_en                       :1; /*[6], RW, 1'h0, enable signal for ac injection detect, when this ldo is used as charger, this bit should be set to 1*/
        u32  ac_on                                   :1; /*[7], RO, 1'h0, ac injection detect result, 1 effective.*/
        u32  highv_ldo_cc_ibit                       :4; /*[11:8], RW, 4'h0, charger constant current setting bits:
                                                          0000: ~140mA
                                                          0001: ~160mA
                                                          001*: ~180mA
                                                          01**: ~200mA
                                                          1***: ~220mA*/
        u32  highv_chr_finish                        :1; /*[12], RW, 1'h0, charging finish signal, 1: finish
                                                          comes from software, when software detect that the battery is full charged, this bit is set to 1 to disable charger.*/
        u32  reserved0                               :19; /*[31:13], RO, 19'h0, */
    }b;
}t_pmu_ctrl_pwr_base_cfg2;


//kp_wakeup_ctrl, offset:0x9c
typedef union
{
    u32 v;
    struct
    {
        u32  kp_wakeup_pin_en                        :15; /*[14:0], RW, 15'h7FFF, [14:0] for gpio0~gpio14. 0, related gpio pin not selected; 1, related gpio pin selected.*/
        u32  reserved1                               :5; /*[19:15], RO, 5'h0, */
        u32  kp_wakeup_pin_en_2                      :2; /*[21:20], RW, 2'h3, [1:0] for gpio21~gpio20. 0, related gpio pin not selected; 1, related gpio pin selected.*/
        u32  reserved0                               :10; /*[31:22], RO, 10'h0, */
    }b;
}t_pmu_ctrl_kp_wakeup_ctrl;

typedef struct
{
    volatile    t_pmu_ctrl_pm_fsm_status                pm_fsm_status;
    volatile    t_pmu_ctrl_pwr_sys_ctrl                 pwr_sys_ctrl;
    volatile    t_pmu_ctrl_pm_fsm_ctrl                  pm_fsm_ctrl;
    volatile    t_pmu_ctrl_xtal_clk32k_div              xtal_clk32k_div;
    volatile    t_pmu_ctrl_xtal_cfg_ctrl0               xtal_cfg_ctrl0;
    volatile    t_pmu_ctrl_xtal_cfg_ctrl1               xtal_cfg_ctrl1;
    volatile    t_pmu_ctrl_pwr_base_cfg                 pwr_base_cfg;
    volatile    t_pmu_ctrl_buck_ctrl                    buck_ctrl;
    volatile    t_pmu_ctrl_ldo_vspi_ctrl                ldo_vspi_ctrl;
    volatile    t_pmu_ctrl_ana_status                   ana_status;
    volatile    t_pmu_ctrl_pmu_ana_rsvd                 pmu_ana_rsvd;
    volatile    t_pmu_ctrl_sw_rsvd                      sw_rsvd;
    volatile    t_pmu_ctrl_misc_ctrl                    misc_ctrl;
    volatile    t_pmu_ctrl_sys_ctrl_protect             sys_ctrl_protect;
    volatile    t_pmu_ctrl_protect                      pmu_ctrl_protect;
    volatile    t_pmu_ctrl_pd_sys_frc_ctr               pd_sys_frc_ctr;
    volatile    t_pmu_ctrl_iomux_cfg0                   iomux_cfg0;
    volatile    t_pmu_ctrl_iomux_cfg1                   iomux_cfg1;
    volatile    t_pmu_ctrl_iomux_cfg2                   iomux_cfg2;
    volatile    t_pmu_ctrl_iomux_cfg3                   iomux_cfg3;
    volatile    t_pmu_ctrl_iomux_cfg4                   iomux_cfg4;
    volatile    t_pmu_ctrl_iomux_cfg5                   iomux_cfg5;
    volatile    t_pmu_ctrl_lpcomp_ctrl                  lpcomp_ctrl;
    volatile    t_pmu_ctrl_lpo32k_xtal32k_ctrl          lpo32k_xtal32k_ctrl;
    volatile    t_pmu_ctrl_rtc_calib_ctrl0              rtc_calib_ctrl0;
    volatile    t_pmu_ctrl_rtc_calib_ctrl1              rtc_calib_ctrl1;
    volatile    t_pmu_ctrl_rtc_calib_status             rtc_calib_status;
    volatile    t_pmu_ctrl_wakeup_ctrl                  wakeup_ctrl;
    volatile    t_pmu_ctrl_wakeup_status                wakeup_status;
    volatile    t_pmu_ctrl_free_timer_cfg_0             free_timer_cfg_0;
    volatile    t_pmu_ctrl_free_timer_cfg_1             free_timer_cfg_1;
    volatile    t_pmu_ctrl_free_timer_cfg_2             free_timer_cfg_2;
    volatile    t_pmu_ctrl_free_timer_status            free_timer_status;
    volatile    t_pmu_ctrl_efuse_auto_rd                efuse_auto_rd;
    volatile    t_pmu_ctrl_force_pm                     force_pm;
    volatile    t_pmu_ctrl_cal_clk_ctrl                 cal_clk_ctrl;
    volatile    t_pmu_ctrl_pd_sys_frc_ctr2              pd_sys_frc_ctr2;
    volatile    t_pmu_ctrl_iomux_cfg6                   iomux_cfg6;
    volatile    t_pmu_ctrl_pwr_base_cfg2                pwr_base_cfg2;
    volatile    t_pmu_ctrl_kp_wakeup_ctrl               kp_wakeup_ctrl;
}t_hwp_pmu_ctrl;

#endif
